Sr Principal RTL Design Engineer
Talentmate
India
18th October 2025
2510-7214-188
Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- 12+ years of experience in ASIC design
- Proficient in Verilog coding, RTL design and complex control path and data path designs
- Knowledge of any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, SATA
- Knowledge of RTL checks ex- LINT, SDC, CDC Familiar with synthesis flow, LEC and timing constraints
- Experience in writing Verilog testbench and running simulations.
Job Details
| Role Level: | Mid-Level | Work Type: | Full-Time |
|---|---|---|---|
| Country: | India | City: | Bengaluru ,Karnataka |
| Company Website: | http://www.cadence.com | Job Function: | Engineering |
| Company Industry/ Sector: |
Software Development | ||
What We Offer
About the Company
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