Senior IP Verification Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

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MTS Design Verification Engineer

 

The Role

As an MTS Design Verification Engineer in AMD’s Infinity (Data) Fabric team, you will be responsible for developing, implementing, and executing advanced verification methodologies to ensure the quality and correctness of AMD’s high-performance interconnect IP. You will work closely with architects, designers, and verification peers to deliver a robust and scalable verification environment for AMD’s CPUs, GPUs, and APUs.

 

THE PERSON: 

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

 

KEY RESPONSIBILITIES: 

• Develop UVM-based verification environments in SystemVerilog for Data Fabric IP blocks and subsystems.
• Create and execute test plans based on architectural and micro-architectural specifications.
• Write constrained-random and directed tests to verify functionality, corner cases, and performance features.
• Define, collect, and analyze functional and code coverage metrics; drive coverage closure.
• Debug simulation failures, working closely with design and architecture teams to root-cause issues.
• Implement checkers, assertions, and monitors to ensure protocol and design compliance.
• Maintain and enhance verification infrastructure for reusability across projects.
• Collaborate with team members across geographies to integrate and verify at the block and subsystem level.
  
  
  

• Strong SystemVerilog and UVM skills for functional verification.
• Experience with functional coverage, random stimulus generation, and assertion-based verification.
• Proficiency with industry-standard EDA tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).
• Solid understanding of computer architecture and digital logic design.
• Strong debugging skills using simulation tools and waveforms.
• Scripting skills in Python, Perl, or similar for automation and regression management
  
  
  

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 5-8 years of experience in ASIC or SoC design verification.
• Experience with multi-clock domain designs, high-speed interconnect protocols, and coherency protocols.
• Familiarity with formal verification methodologies is a plus.