Design Verification Engineer III Multimedia Silicon

Minimum qualifications:

• Bachelors degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 4 years of experience verifying digital logic at RTL using SystemVerilog for ASICs.
• Experience verifying digital systems using standard IP components/interconnects (microprocessor cores or hierarchical memory subsystems).
• Experience with object-oriented programming.
  
  

Preferred qualifications:

• Masters or PhD degree in Electrical Engineering or Computer Science.
• Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification.
• Experience creating and using verification components and environments in a standard verification methodology (e.g., UVM).
• Experience with image processing or other multimedia IPs, such as display or video codec.
• Experience with ASIC components, standard interfaces, performance verification, and memory system architecture.
  
  

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Googles direct-to-consumer products. Youll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The Platforms and Devices team encompasses Googles various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our users interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Plan the verification of complex multimedia digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using System Verilog and UVM.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with Design Engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.
  
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Googles EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

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