ASIC Design Engineer - Performance Monitoring

NVIDIA System-On-Chip (SOC) group is hiring for a Design Engineer! The complexity of the chips we build has increased manifold over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand. We are looking for a top ASIC Design Engineer. In this role, you should have real passion for RTL design implementation and methodologies that enable high quality system-level IP design.

What Youll Be Doing

• Be an integral part of the team defining and developing system-level RTL and methodologies to measure performance on the industrys leading GPUs/SOCs.
• Design and implement RTL features - work through the entire design cycle for SOC.
• Run and debug RTL checks to ensure design quality (e.g. CDC, RDC, Lint, Synthesis, Logic-Equivalence and more)
• Define, develop, and automate flows and methodologies to efficiently build and support a system-level IP
• Work with architects, designers, verification and SW engineers to accomplish your tasks.
  
  

• B.Tech or M.Tech in Electronics or Computer Engineering.
• 2+ years of relevant industry experience.
• Experience in RTL design (Verilog), System-On-Chip design/implementation flow, and design automation.
• Good understanding of SOC architecture (e.g., CDC, multiple-power domains, performance analysis, latency, and data flow).
• Strong coding skills in Perl, Python or other industry-standard scripting languages.
• Excellent debugging and analytical skills.
• Exposure to design and verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, debug tools like Debussy, GDB).
• Exposure to AI tools is a plus
• Great communication and collaboration skills to interact within the team and with cross functional teams