Design Verification Engineer

The Opportunity

Were looking for the Wavemakers of tomorrow.

Alphawave Semi enables tomorrow’s future by accelerating the critical data communication at the heart of our digital world – from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology.

Our IP Scaling (IPS) organization is focused on creating customized IP for Alphawave Semis expanding customer base. We deliver industry-leading high-speed interconnect solutions tailored to specific requirements across a wide variety of use-cases including High Performance Computing and Artificial Intelligence. We are looking for an enthusiastic Design Verification Engineer to join our fun and dynamic team of experienced innovators.

What youll do:

• Own the end-to-end verification of new customer features
• Review design specifications and devise verification plans
• Build testbenches and analyze test failures to uncover design bugs
• Facilitate bit-matching of RTL design and MATLAB system models
• Integrate 3rd party VIPs for compliance testing of standard protocols
• Build releases of our design IP for customers
• Support post-silicon validation and bring-up activities
• Take on opportunities to lead, plan, and coordinate tasks with team members
• Collaborate closely with Design, Systems, Analog, FW, and PD teams
• Contribute to the continuous improvement of verification methodologies and processes
  
  
  

• 5+ years of ASIC design verification experience
• An applied understanding of UVM and verification techniques
• Experience with constrained-random verification in SystemVerilog and UVM
• Formal Verification, and Power-aware UPF verification techniques
• Tools/Languages - SystemVerilog, UVM, Python, Perl, C/C++, GNU Make
• Verification experience in SerDes PHY, DSP, and Analog mixed signal is desirable
• Knowledge in Ethernet and PCIe standards is desirable
  
  
  

• Competitive Compensation Package
• Restricted Stock Units (RSUs)
• Provisions to pursue advanced education from Premium Institute, eLearning content providers
• Medical Insurance and a cohort of Wellness Benefits
• Educational Assistance
• Advance Loan Assistance
• Office lunch & Snacks Facility