MTS Synthesis Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

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MTS SILICON DESIGN ENGINEER 

 

The Role

As part of AIG silicon team, you will have opportunity to work with some of the most talented and passionate engineers to create designs that push the performance, efficiency and scalability. We offer a fun, creative and flexible work environment with a shared vision to build products changing the world.

 

THE PERSON: 

As a Synthesis design engineer, you will work with architects/designers for IP development

 

KEY RESPONSIBILITIES: 

• Design synthesis: Performing logical and physical synthesis of blocks in IP
• Design analysis: Analyzing and verifying that the design meets requirements for functionality, performance, and area
• Design constraints: Defining synthesis design constraints and resolving STA issues
• Timing analysis: Analyzing timing arc and liberty quality, and providing suggestions for fixing timing violations
• Design quality checks: Completing all design quality checks and data quality checks (CDC/RDC/LINT/No clock flops etc)
• Collaboration: Working with RTL engineers to fix timing issues
• Tool evaluation: Driving new tool evaluation and methodology refinement
• ECO Implementation :Develop/enhance auto ECO generation scripts for timing closure and ECO implementation
• Power: Low power optimizations/UPF
  
  
  

• Synopsys tools for ASIC synthesis and timing constraints
• Strong background in Timing analysis and CDC
• Experience in CDC/RDC/LINT closure
• Familiar with power intent definition, implementation (UPF)
• Knowledge of various implementation and architectural techniques for low power optimization.
• Verilog and System Verilog
• Perl/TCL/Makefile scripting
• Power Analysis using Power Artist and PTPX
• LEC, LP signoff tools
• VLSI front end design steps
• Good communication skills and ability to work with global teams
  
  
  

• Bachelors or Masters degree in computer engineering/Electrical Engineering and 7+ years of work experience