Lead Full Chip Timing STA Expertise

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PMTS SILICON DESIGN ENGINEER

The Role

The position will involve working with a very experienced physical design team of Server SOC and is responsible for full chip timing, constraints and signoff s to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology.

 

The Person

Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones.

Key Responsibilities

• Working on full chip static timing analysis setup and signoff of multi-corner multi-voltage designs, constraints,
• Owning timing execution to meet timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management
• Areas of focus include Timing analysis and verification, extraction and noise glitch analysis, Constraints
• Engaging closely with Design teams to understand the design and convergence challenges and providing ECOs with a focus on PPA and TAT optimizations.
• Hierarchical timing analysis and convergence at block, section and fullchip level.
• Understanding CTS strategies, LVF/POCV variations and providing feedback to the implementation/methodology teams.
  
  
  

• 16+ years of professional experience in Constraints generation, STA, full chip timing and physical design, preferably with high performance designs.
• Demonstrated ability in areas of Timing analysis, timing convergence, SI/Noise analysis, Signoff quality (PVT, process variation effects, guardbanding, etc), Timing ECOs, PV/Noise modelling, .libs, is a must.
• Multi-voltage scenarios design handling knowledge is expected. STA closure/convergence execution on Low power designs is an added advantage.
• Expertise in industry standard EDA tools (Primetime)
• Hands-on experience with Physical Design implementation is a plus
• Proficiency in scripting language, such as, Perl and Tcl.
• Versatility with scripts to automate design flow, analysis
• Strong communication skills, ability to multi-task across projects, and work with geographically spread-out teams
• Experience in 16/14/10/7/5/3nm nodes
• Good understanding of computer organization/architecture is preferred.
• Strong analytical/problem solving skills and pronounced attention to details
  
  
  

• Bachelor’s or Master’s degree in related discipline preferred