Lead DFT Engineer

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Lead DFT Engineer

The Role

Lead DFT engineer will lead strong engineering team on Scan, MBIST, iJTAG test development of latest AMD products. The IPs range from complex processors, AI computation blocks, to state-of-the-art controller IPs which provide automotive, data center, machine learning and high-speed communication solutions. You will work closely with designers to make sure DFT structures are correctly implemented, with test engineers to make sure ATE test programs can be generated from the DFT (ATPG, MBIST) tools, with product engineers to make sure scan/mbist production test can run seamlessly and stable, and with yield engineers to debug and root-cause failures/defects. You will get the opportunity to expand technical knowledge beyond DFT into embedded processor firmware, complex chip simulation, RTL implementation for ASIC & FPGA and deep silicon debug work all the way to high-volume production requirement. This is the role to oversee complete silicon cycle from design to production phases.

The Person

We are looking for candidates that can communicate complex engineering subjects effectively to cross functioning technical teams and upper management. Strong DFT and leadership skills will be put to good use. Successful Senior Member of Technical Staff DFT engineer will interact with many external teams and must confidently represent his/her organization.

Key Responsibilities

• Manage DFT engineers resolving technical challenges and meeting product schedule
• The role is in AMD global quality and operation organization driving best manufacturing test solution through pre and post silicon activities
• Work closely with design teams and make sure DFT structures are correctly implemented.
• Responsible for developing, implementing and verifying DFT schemes on hard-IPs in AMD ASIC and FPGA products.
• Responsible for developing and implementing techniques to test digital logic, using Scan Compression, Stuck-at, Transition and Path-Delay fault models
• Responsible for testing other parts of the design, including memory, mixed-signal, I/Os, custom LBISTs & MBISTs, IEEE1149.1 JTAG and IEEE1687 IJTAG
• Responsible to develop Firmware driven cost-effective test strategies/methodologies with built-in diagnosis capability to enable efficient debugging and fault isolation on bench/ATE
• Collaborate closely with the New Product Introduction and Test/Product teams to ensure timely delivery of robust test patterns, and manage debugging of pattern issues on bench/ATE to root cause the problem
• Assist in Diagnosis and Yield enhancement through product lifecycle
• Develop an adaptive and cohesive team to take up any challenging tasks entrusted by management
  
  
  

• Over 15 years of DFT engineering experience through DFT pre and post silicon cycles
• Experience in creating and implementing complex chip-level DFT architecture
• Experience in DFT implementation including Scan and Scan Compression at IP and SoC level
• Experience with DFT tools, ATPG (Stuck-At, At-Speed, Path-Delay) and scan compression.
• Strong MBIST knowledge
• Knowledge of Tessent Streaming Scan Network SSN and hand-on experience is a big plus
• Proficient in logic design using Verilog and experience in synthesis and STA
• Experience in developing test benches and simulation in RTL/GATE/SDF environments
• Knowledge of FPGA synthesis and design flow is a plus
• Experience with post-silicon debug and bench equipment (e.g., oscilloscope and logic analyser)
• Good communication skills, works well in a group environment that spans across continents
• Comfortable in Linux environment and writing/using scripting languages such as Perl, Tcl, etc
  
  
  

• MS or Ph.D. in Electrical/Electronic/Computer Engineering