Post Silicon Validation- Staff

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced and highly motivated individual with a passion for technology and innovation. You have a strong technical background in RTL, Physical Design, and post-silicon test and testability development. Your expertise in debugging and developing Process, Voltage, Temperature, Current, and Droop sensors is unparalleled. You thrive in a dynamic environment and excel in communication, teamwork, and leadership. You are eager to learn and contribute to the development of state-of-the-art PVT IP sensors that are integral to the silicon lifecycle monitoring process. You possess a mindset geared towards meticulous IP debug and documentation, ensuring the highest standards of product development and performance.

What You’ll Be Doing:

• Serving as the single point of contact for post-silicon debug activities.
• Enabling Product Requirement Documents (PRDs).
• Working to enable IP as a product development platform.
• Handling hands-on post-silicon test setups.
• Collaborating on top-level physical design, board-level, and package-level designs.
• Developing post-silicon reports and conducting debug analysis.
  
  

• Driving the successful development and deployment of PVT IP sensors.
• Enhancing the reliability and performance of Synopsys silicon lifecycle monitoring solutions.
• Ensuring high-quality product development through meticulous testing and debugging.
• Contributing to the continuous innovation in chip design and software security.
• Supporting Synopsys leadership in the market for PVT IP developments.
• Empowering the creation of high-performance silicon chips used in various advanced technologies.
  
  

• Hands-on experience in post-silicon test setups.
• Sound knowledge of Digital/AMS chip design and post-silicon debug.
• BS or MS degree in Electrical Engineering with 5+ years of experience.
• Understanding of top-level physical design, board-level, and package-level designs.
• Expertise in RTL development and physical design.
  
  

• Strong communicator with excellent teamwork and interpersonal skills.
• Detail-oriented with a mindset geared towards IP debug and documentation.
• Proactive learner with the ability to adapt to new IP functionalities.
• Highly motivated and capable of mentoring both internal teams and external customers.