Thought Frameworks - DFT Lead

Position : DFT Lead

Experience : 5-9 Years

Location : Bangalore

Work Mode : Work from office

Work Type : Contract

Job Summary

We are seeking a highly skilled and experienced DFT (Design for Testability) Lead with 5-9 years of experience to join our team in Bangalore.

The ideal candidate will be a hands-on expert in leading scan insertion and ATPG (Automatic Test Pattern Generation) flows for complex digital designs.

This role is crucial for ensuring the testability, quality, and manufacturability of our chips by optimizing test coverage and debugging test failures.

The position is a contract role that requires the ability to work on-site and the flexibility for a face-to-face interview.

Key Responsibilities

• DFT Architecture & Implementation : Lead the end-to-end scan insertion and ATPG flow for digital blocks, from initial design to final sign-off.
• Test Coverage Optimization : Take ownership of reviewing and optimizing test coverage metrics to ensure a high level of fault detection and a low defect rate.
• DFT Integration & Debugging : Integrate complex DFT solutions into the overall chip design.
  
  

• Performance & Reporting : Analyze and report on key test metrics, providing clear and concise updates to upper management on the status of DFT implementation and test coverage.
• Tool & Scripting Proficiency : Utilize and be proficient with a range of industry-standard test tools and develop automation scripts to enhance efficiency.
  
  

• 5-9 years of relevant experience in DFT roles.
• Expert-level knowledge of ATPG and fault coverage analysis.
• Proven experience with scan insertion methodologies and tools.
• Strong hands-on experience with DFT test tools.
• Proficiency in scripting languages for automation.
  
  

• Experience with various DFT structures such as JTAG and MBIST.
• Knowledge of other design verification methodologies.
• Strong problem-solving and debugging skills in a complex silicon design environment