IP Subsystems Design Verification Lead

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SMTS SILICON DESIGN VERIFICATION ENGINEER 

 

The Role

As a member of the Computing and Graphics group, you will help bring to life cutting-edge designs. As a member of the front-end design verification team, you will work closely with architecture, IP design and SOC verification engineers to achieve first pass silicon success.

Design Verification Engineer

The Person

The ideal candidate will have experience verifying RTL for IP or subsystems and understand architectural specifications. Responsibilities include IP and subsystem design verification and working collaboratively with the IP/SoC team.

Key Responsibilities

• Verification of IP and subsystems for AMD and other 3rd party IPs
• Create test plans, develop testbenches, write constrained random test cases, perform code coverage analysis, create coverpooints and analyze functional coverage.
• Work collaboratively with other members of the IP team to support design implementation for IP delivery to SOC
• Work in partnership with SOC teams to support the IP at SOC level, including SOC verification, performance testing, software, firmware, and post-silicon bring-up
  
  
  

• 8-12 years full-time experience in RTL design verification
• Proficiency in system verilog and UVM for digital design verification
• Code coverage analysis and how to close line, expression and branch coverage
• Experience with assertion-based verification (ABV)
• Detailed knowledge of how to code coverpoints and closing functional coverage in a constrained random environment
• Experience with embedded processors and data fabric architectures
• Outstanding interaction skills while communicating both written and verbally
• Ability to work with multi-level functional teams across various geographies
• Outstanding problem-solving and analytical skills 
  
  
  

• Bachelors degree in Computer Engineering/Electrical Engineering plus 12 years full-time experience in IP hardware design, or Masters degree plus 8 years experience in same.