Design Verification Engineer Lead

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SMTS SILICON DESIGN ENGINEER

The Role

This is a ASIC Hardware and Firmware Co-Verification Engineering role with the Security IP Team (SECIP). The primary focus of this role is to Lead the team responsible for Hardware/Firmware co-verification of various embedded micro-processor subsystems and the associated hardware accelerators in leading edge SOC’s. The preferred candidate will also have proven experience in Firmware development and the ability to contribute to Firmware development initiatives. These IP subsystems provide high performance functions to the respective SoC, such as security policy management, cryptography, data compression, high throughput DMA, etc.

The Person

You will have strong analytical/problem solving skills, high attention to detail, and motivation to independently drive tasks to completion. You will also have professional interpersonal and communication skills. If this sounds like a role you are interested in, we welcome you to apply!

Key Responsibilities

• Development and verification of embedded firmware for SOC secure boot and embedded microprocessor driven hardware acceleration services for cryptography, decompression and large scale DMA functions.
• Hardware/Firmware co-verification in UVM System Verilog and C-DPI structured testbench.
• Hardware/Firmware co-verification in FPGA hardware prototype platform.
• Develop and maintain subsystem verification architecture, testbench, test methodology for
• Embedded CPU and subcomponent IPs with
• AXI/AHB busses and HW accelerators such as
• Cryptography, Data Compression, DMA, etc.
• Participate in subsystem specification, influence IP micro-architecture development (HW and FW co-design and verification aspect), develop and verify abstracted performance model
• Create abstracted FW and HW performance models
• Develop critical target code to collect IP performance key parameters
• Explore subsystem architecture performance trade-off for FW and HW optimization
• Develop and execute subsystem and block level test plans
• Develop FW/HW co-verification methodology
• Develop UVC and System Response models
• Develop and debug UVM and C-DPI test cases with integrated FW
• Improve verification metrics
• Further develop subsystem and block level testbenches using UVM randomized test methodology and C-DPI directed test methodology.
• Develop and maintain subsystem level integration scripts
• Develop and maintain subsystem testbench build and test run scripts
• Drive to verification metrics closure
• Interface with SoC integration and SoC DV teams
• Define and develop IP level DV API to support SoC level DV effort
• Develop and maintain IP build and delivery infrastructure to support SoC level integration of SMU IPs.
• Support SoC level IP emulation, silicon bring-up and debugging effort
  

• ASIC FW and HW design and verification experience
• Proficient in C, C++, Assembly, Verilog, System Verilog, and several scripting languages (Make, Perl, Python, etc.)
• Excellent knowledge about UVM methodology and C-DPI methodology
• Excellent knowledge about standard bus/interface protocols (i.e. AXI, AHB, AMBA)
• Excellent experience with firmware design on commercial microprocessors
• Excellent experience with microprocessor tool chain, compiler, assembler, debugger
• Excellent experience with ASIC verification tools, simulation, linting, power aware simulation, etc.
  
  
  

• Major in Electrical or Computer Engineering.
• B.Eng or Master’s or PhD Degree preferred.