GPIO Circuit Design Engineering Manager

Title: GPIO Circuit Design Engineering Manager

About GlobalFoundries

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Job Summary

The GPIO Manager will lead the design, development, and delivery of GPIO IP blocks and related IO subsystems for advanced semiconductor products. This role involves cross-functional collaboration with architecture, design, verification, physical design, and product engineering teams to ensure high-quality, robust, and scalable IO solutions.

Key Responsibilities

• Define GPIO architecture and specifications in collaboration with system architects.
• Lead a team of design and verification engineers to deliver GPIO IP blocks.
• Manage project schedules, deliverables, and resource allocation.
• Ensure compliance with industry standards (e.g., JEDEC, IEEE) and internal quality metrics.
• Interface with SoC integration teams to support GPIO integration and debug.
• Drive innovation in IO design for power, performance, and area optimization.
• Collaborate with EDA vendors and internal CAD teams for tool flows and methodology improvements.
• Support silicon bring-up and validation of GPIO functionality.
• Provide technical leadership and mentorship to junior engineers.
  
  

Required Skills & Qualifications

• Bachelors or Masters degree in Electrical Engineering, Electronics, or related field.
• 15+ years of experience in semiconductor IP design, with at least 3 years in a leadership role.
• Deep understanding of digital and mixed-signal IO design principles.
• Knowledge of process technology impact on circuit design is a plus
• High Speed I/O Design is also plus.
• Experience with RTL design (Verilog/VHDL), synthesis, and timing closure.
• Familiarity with ESD, pad ring design, and physical verification flows.
• Strong project management and communication skills.
• Experience with silicon validation and lab debug tools is a plus.
  
  

Preferred Qualifications

• Prior experience managing GPIO or similar IO IP blocks.
• Knowledge of low-power design techniques and IO reliability.
  
  

GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard.  

As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. 

All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. 

Information about our benefits you can find here: https://gf.com/about-us/careers/opportunities-asia

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