Staff STA Static Timing Analysis Engineer

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is looking for a skilled and detail-oriented Static Timing Analysis (STA) Engineer to help us deliver first-pass silicon success for our cutting-edge AI and RISC-V SoCs. In this role, you’ll lead timing closure efforts across block and full-chip levels, working closely with physical design, RTL, and verification teams across multiple technology nodes, including 5nm and 3nm.

This role is onsite, based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Have hands-on experience in STA for complex SoCs, from block to full-chip level.
• Comfortable using tools like PrimeTime, Tempus, or PTPX.
• Strong in scripting with Tcl, Perl, or Python to automate workflows.
• Confident working cross-functionally to solve timing challenges and drive closure.
  
  

• Ability to define and drive STA methodology across different corners and modes.
• Skill in analyzing timing reports and working across teams to fix violations.
• Experience with timing constraints, CDC analysis, and low-power techniques.
• Familiarity with MMMC flows, ECO handling, and debugging timing exceptions.
  
  

• The art of navigating timing closure on advanced nodes like 5nm and 3nm.
• How to collaborate across global teams to deliver high-performance silicon.
• Best practice in improving STA signoff processes and checklists in a fast-paced environment.
• Ways to sharpen your debugging skills with real silicon use cases and first-silicon success targets.