Sr Staff STA Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced and driven professional with a strong technical background in Static Timing Analysis (STA) and physical design at the IP, block, and full-chip levels. You excel in tackling challenges associated with advanced FinFET and GAA processes and have a proven ability to deliver high-quality results in complex design environments. Your expertise spans RTL-to-GDS implementation, timing closure, and signoff methodologies, and you are adept at collaborating with cross-functional teams to achieve optimal design solutions.

You are detail-oriented, proactive, and thrive in a collaborative environment where innovation and continuous improvement are valued. Your strong communication skills enable you to effectively engage with internal teams and external customers, ensuring alignment and success in project execution. With a passion for technology and a commitment to excellence, you are eager to contribute to the development of cutting-edge semiconductor solutions that shape the future.

What You’ll Be Doing:

• Conceptualizing, designing, and productizing state-of-the-art RTL-to-GDS implementations for SLM monitors using ASIC design flows.
• Designing on-chip Process, Voltage, Temperature, Glitch, and Droop monitors to track silicon biometrics.
• Developing digital back-end activities, including synthesis, pre-layout STA, SDC constraints development, placement, CTS, and routing, while collaborating with functional teams to achieve optimal design solutions.
• Performing post-layout STA, timing and functional ECO development, and timing signoff for high-frequency IP designs.
• Collaborating with the Place & Route team to resolve full-chip/IP/block-level layout integration issues and drive timing closure.
• Coordinating with internal RTL IP owners to address constraints-related issues.
• Creating and updating flows/methodologies in collaboration with architects, physical design, and RTL design engineering teams.
• Ensuring pre-layout and post-layout timing closure and timing model characterizations across various design corners to meet reliability and aging requirements for automotive and consumer products.
  
  

The Impact You Will Have:

• Accelerating the integration of next-generation intelligent in-chip sensors and analytics into cutting-edge technology products.
• Optimizing performance, power, area, schedule, and yield across semiconductor lifecycle stages.
• Enhancing product reliability and differentiation in the market while reducing risk.
• Driving innovation in STA and signoff design methodologies and tools.
• Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions.
• Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies.
  
  

What You’ll Need:

• Educational Background: BS/B.Tech or MS/M.Tech in Electrical Engineering with 5+ years of relevant industry experience.
• Technical Expertise:
• Strong experience in physical design, pre- and post-layout STA, and signoff, including SDC development and multi-mode design development.
• Proven expertise in functional and test constraints development (shift, capture, and at-speed) and timing closure with MCMM.
• Experience in generating ECOs for DRV cleaning and timing closure.
• Proficiency with digital design tools from any EDA vendor, preferably Synopsys tools like FC/PT/PT-PX.
• Solid understanding of OCV, POCV, derates, crosstalk, and design margins.
• Advanced Node Experience: Successful timing closure and tape-outs in advanced nodes (14nm, 10nm, 7nm, 5nm, 3nm, 2nm).
• Scripting Skills: Experience in scripting with TCL/PERL for developing custom scripts and enhancing design flows.
  

Who You Are:

• Proactive and detail-oriented with excellent problem-solving skills.
• Adept at working independently and providing physical design and signoff solutions.
• A strong communicator and team player, capable of collaborating effectively with diverse teams.
• An innovative thinker with a passion for technology and continuous improvement.
• Committed to delivering high-quality results and achieving project goals.
  
  

The Team You’ll Be A Part Of:

You will join a dynamic and collaborative team of engineers focused on developing cutting-edge semiconductor solutions. The team works on advanced STA methodologies, physical design, and signoff processes, driving innovation and excellence in the development of next-generation technology products. Together, you will tackle complex challenges, push the boundaries of technology, and contribute to the success of Synopsys industry-leading solutions.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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