Tech Lead Verification Methodology CAD

TechLead– Verification Methodology / CAD / Automation Engineer 

Experience - 6–12 years 

Job Summary 

We are looking for a Tech Lead – Verification Methodology/CAD/Automation Engineer to drive verification infrastructure, methodology, automation, and productivity across IP and SoC verification teams. 

The candidate will build scalable verification frameworks, automate verification workflows, improve regression infrastructure, and partner with design verification teams to establish efficient and reusable methodologies. 

Key Responsibilities 

• Own and drive verification methodology and infrastructure across projects. 

• Develop scalable frameworks for simulation, regression, coverage, debug, and verification signoff. 

• Build and maintain verification CAD/automation flows. 

• Develop automation scripts and tools using Python, Tcl, Perl, Shell, and/or C++. 

• Automate test generation, compilation, regression execution, result collection, coverage analysis, and reporting. 

• Develop infrastructure for large-scale UVM/SystemVerilog verification environments. 

• Improve simulation and regression turnaround time through parallelization and optimization. 

• Integrate simulation, lint, CDC/RDC, formal, coverage, and other verification tools into common workflows. 

• Develop dashboards and metrics for verification quality, coverage, regression health, and project status. 

• Debug infrastructure and tool-flow issues and provide rapid support to verification teams. 

• Establish reusable verification components, scripts, libraries, and methodology guidelines. 

• Drive adoption of best practices across multiple verification teams. 

• Evaluate new verification technologies and tools and recommend improvements. 

• Work closely with EDA vendors to troubleshoot tool issues and improve flows. 

• Support migration and integration of new EDA tool versions and methodologies. 

• Develop documentation and training for verification teams. 

• Mentor verification CAD/methodology engineers and provide technical leadership. 

Required Technical Skills 

• Strong experience in verification methodology, CAD, and automation. 

• Strong programming/scripting skills in Python, Tcl, Perl, Shell, and preferably C/C++. 

• Strong understanding of SystemVerilog/UVM. 

• Experience with simulation tools such as VCS, Xcelium, Questa, or equivalent. 

• Experience building and maintaining regression infrastructure. 

• Strong knowledge of coverage collection and analysis. 

• Understanding of verification flows including: 

• Simulation 

• UVM 

• Lint 

• CDC/RDC 

• Formal 

• Code/functional coverage 

• Regression 

• Debug 

• Strong Linux/Unix environment experience. 

• Excellent automation and problem-solving skills. 

Preferred Experience 

• Experience with large-scale SoC/IP verification environments. 

• Experience integrating multiple EDA tools into a unified verification flow. 

• Experience with CI/CD infrastructure such as Jenkins, GitLab CI, or equivalent. 

• Experience with distributed/parallel regression infrastructure. 

• Experience with cloud-based or scalable compute environments. 

• Knowledge of databases, dashboards, APIs, or web-based verification infrastructure is an advantage. 

• Experience working with EDA vendors and managing tool-flow issues. 

Leadership Expectations 

• Act as the technical owner for verification methodology and automation. 

• Identify opportunities to improve verification productivity, quality, and turnaround time. 

• Define and enforce verification methodology standards. 

• Mentor engineers and drive adoption of common frameworks. 

• Work across multiple projects and teams to solve infrastructure challenges. 

• Strong ability to balance immediate project requirements with long-term methodology improvements. 

Education 

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Science, Computer Engineering, VLSI, or a related discipline.