Senior Designer Layout

About Analog Devices

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).

Senior Designer, IC Layout

SUMMARY:

ADI’s Joint Development Team (JDT) is looking for dynamic and enthusiastic individuals to fill the role of Senior Designer, Layout. The Joint Development Team is a small, independent, cross-disciplinary group working within the Data Center & Energy division of Analog Devices. Its charter is to accelerate the development of key components, systems, algorithms, and techniques necessary to advance the state of the art in targeted areas within this market segment and to collaborate with focused product development teams to get these advances to the marketplace. Current, past and future research areas include energy metering & fault detection, advanced medical devices, security electronics, imaging, ultra-precision references and data converters.

The group is led by Analog Devices Fellow JED Hurwitz, a pioneer in CMOS imaging, recognized expert in ultra-high precision and energy systems, and of broad industrial experience. He encourages “layout driven design” and has enormous personal experience of layout. Few, if any, ADI Fellows are more passionate about the importance of layout in product development. The group culture aims to foster a challenging, exciting, and supportive environment.

The Senior Designer, Layout is mainly responsible for the creation of section level layouts. He/she will mostly work with schematic designers, block layout resources and lead layout people. His/her job is to meet schedule, design and quality requirements set by project stakeholders. Depending on the project size, he/she will be handling several block layout resources, and it will be his/her task to allocate tasks, set schedule and provide direction. He/she will have the opportunity to mentor new hires or interns and may likewise be tapped to be a part of other development initiatives for the layout team.

JDT is expanding its presence and growing its footprint in the Philippines to enable complete front‑end product development, from architecture through first silicon. We are expanding across analog, digital, verification, and layout disciplines to support advanced mixed signal‑signal products in precision sensing, imaging, and security applications. This expansion represents a long‑term investment in senior technical talent and leadership roles within ADI Philippines.

KEY QUALIFICATIONS:

• Extensive section (multi-hierarchical) level layout experience
• Top/Chip level layout is an advantage
• Strong fundamental knowledge in semiconductor device physics, cross-section and construction
• Strong fundamental knowledge in layout principles, IC reliability and failure mechanisms
• Proficiency in Cadence Virtuoso XL and Calibre verification tools is an advantage
  

• BS Electronics or Electrical Engineering
• At least 5 years of relevant working experience
  
  

• Strong communications skills, both oral and written
• Able to work and effectively collaborate with a cross-functional and global team
• Strong leadership skills are an advantage
• Layout experience in any of the following areas is an advantage: ADC, DAC, array-based layout, and high-voltage applications
• Layout experience in various processes, (40nm, 180nm and others)
• Experience of tape out, assembly and interfacing with the foundries is an advantage.