Principal Engineer- ASIC Digital Design Die To Die Communication Protocol

Principal ASIC Design Engineer – Die-to-Die Protocols; Location: Noida/Pune

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned digital design professional with a passion for architecting and implementing state-of-the-art ASIC solutions. Bringing over a decade of hands-on experience in RTL design, you thrive in complex, multi-site environments and are driven by the challenge of building high-performance IP Cores for consumer and automotive applications. Your expertise spans industry protocols such as UCIe, Ethernet, PCIe, DDR, and more, making you a go-to technical leader for die-to-die communication solutions.

You possess a strong foundation in HDL design flows and have mastered tools including Verilog/SystemVerilog, synthesis, CDC analysis, and static timing. Your background includes the ability to define and drive micro-architectures from functional specifications, and you excel at balancing innovation with quality-driven processes. As a mentor and collaborator, you inspire teams to achieve technical excellence, and your communication skills allow you to interface seamlessly with global colleagues and customers.

You are proactive, detail-oriented, and committed to continuous learning and improvement. Your initiative and problem-solving abilities set you apart, and you are eager to contribute to a culture of innovation at Synopsys. If you’re ready to lead challenging projects and make a tangible impact on next-generation technology, this role is tailored for you.

What You’ll Be Doing:

• Architecting and implementing high-performance RTL designs for advanced IP cores, focusing on die-to-die communication protocols such as UCIe for consumer and automotive applications.
• Creating comprehensive architecture and micro-architecture documents, translating functional specifications into detailed design solutions for complex components.
• Leading and executing design tasks including RTL coding, synthesis, CDC analysis, debugging, and test development, ensuring robust and reliable ASIC designs.
• Collaborating closely with the verification team to plan, execute, and close verification cycles, achieving high coverage and design quality.
• Interacting with customers to clarify specification requirements and ensure design alignment with end-user needs.
• Mentoring and technically leading a team of designers, fostering skill development and knowledge sharing within a global, multi-site environment.
  
  

The Impact You Will Have:

• Delivering cutting-edge IP cores that enable seamless, high-speed communication in next-generation chips for automotive and consumer products.
• Driving architectural innovation and protocol integration, positioning Synopsys as a leader in die-to-die and high-speed communication technologies.
• Ensuring the highest standards of design quality and reliability, contributing to the success of Synopsys customers worldwide.
• Mentoring and uplifting team capabilities, fostering a culture of technical excellence and collaboration.
• Accelerating project timelines and reducing time-to-market for key IP solutions through expert technical leadership.
• Enhancing Synopsys’ reputation for delivering robust, scalable, and innovative silicon solutions in a fast-evolving industry.
  
  

What You’ll Need:

• BSEE or MSEE in Electrical Engineering, with 12+ years of relevant industry experience in ASIC digital design.
• Proficiency in one or more protocols: Ethernet, DDR, Die-to-Die Communication, PCIe, CXL, USB, etc.
• Expertise in micro-architecture, RTL coding (Verilog/SystemVerilog), and design flows for ASIC implementation.
• Hands-on experience with synthesis, CDC analysis, formal checking, and static timing analysis.
• Familiarity with high-speed design, P&R-aware synthesis, and advanced tools such as Fusion Compiler.
• Experience with revision control systems (e.g., Perforce) and scripting languages like Perl/Shell.
• Exposure to quality processes in IP design and verification.
• Demonstrated ability to technically lead and mentor a team of designers.
  
  

Who You Are:

• Innovative and detail-oriented, with a relentless drive for technical excellence.
• Exceptional communicator, adept at collaborating across global teams and with external customers.
• Strong problem-solver who thrives in challenging, fast-paced environments.
• Team player who actively contributes to a collaborative and inclusive culture.
• Natural leader and mentor, inspiring others to achieve their best.
• Proactive and adaptable, always seeking opportunities to learn and improve.
  
  

The Team You’ll Be A Part Of:

You’ll join the DesignWare IP Design R&D team at Synopsys’ Noida/Pune Design Center, collaborating with a diverse group of expert engineers across multiple global sites. The team specializes in developing high-performance, synthesizable IP cores for a wide range of applications, emphasizing innovation, quality, and customer success. You’ll be immersed in a supportive environment that values technical growth, knowledge sharing, and continuous improvement.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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