Sykatiya Technologies - RTL Design Engineer - Static Timing Analysis

About The Role

We are looking for a skilled RTL Design Engineer with strong expertise in RTL coding, Clock Domain Crossing (CDC), linting, and regression checks. The candidate will collaborate closely with Design Verification (DV), Emulation, and Physical Design teams to support design handoffs, optimize design quality, and address timing, area, power, and congestion challenges.

The role involves front-end design implementation, synthesis, formal verification, timing constraint development, and automation of front-end design methodologies.

Key Responsibilities

• Perform logic and physical synthesis using advanced optimization techniques to generate optimized gate-level netlists for timing, area, and power (PPA).
• Analyze and debug timing, area, and congestion issues in collaboration with RTL and Physical Design Engineers.
• Perform power estimation at both RTL and gate levels and identify opportunities for power optimization.
• Execute formal equivalence checks between RTL and gate-level netlists, debugging aborts, inconclusive results, and logic equivalency failures.
• Conduct RTL lint checks, analyze violations, and collaborate with designers to define appropriate waivers.
• Perform RTL Design for Test (DFT) analysis and improve stuck-at fault coverage.
• Develop timing constraints for RTL synthesis and PrimeTime Static Timing Analysis (STA) at block and top-level SoC levels.
• Analyze inter-block timing requirements and establish appropriate I/O timing budgets for partitioned blocks.
• Develop and maintain automation scripts and methodologies for front-end design tools, including Lint, CDC, RDC, synthesis, STA, and power analysis.
• Collaborate with Design, DV, Emulation, and Physical Design teams to ensure smooth design handoffs and resolve implementation issues.
• Support regression checks and ensure design quality, consistency, and readiness for downstream implementation.
  
  

• 5 - 8 years of experience in RTL design and front-end VLSI design methodologies.
• Strong expertise in RTL coding and design quality checks.
• Hands-on experience with RTL lint, CDC, and regression checks.
• Practical experience with logic synthesis and gate-level netlist generation.
• Knowledge of timing analysis, timing constraints, and PrimeTime STA.
• Experience with formal verification and RTL-to-gate-level equivalence checking.
• Understanding of power estimation, area optimization, timing closure, and congestion analysis.
• Knowledge of DFT analysis and stuck-at fault coverage improvement.
• Experience developing automation scripts and methodologies for front-end design tools.
• Strong debugging, analytical, and cross-functional collaboration skills.