Staff Analog Design Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned analog design professional with a passion for pushing technology boundaries. With over a decade of hands-on experience in analog IC design, you thrive in fast-paced, collaborative environments and are motivated by technical challenges. Your expertise in Multi-Gbps NRZ & PAM4 SERDES IP and familiarity with the latest FinFET and gate-all-around process nodes set you apart as a leader in the field. You are adept at translating complex SerDes standards into innovative, high-performance circuit architectures and are comfortable navigating the intricacies of transistor-level design, system-level budgeting, and analog/digital co-design.

You excel at mentoring peers, sharing knowledge, and advocating for design excellence. Your strong analytical skills allow you to quickly identify architectural bottlenecks and propose effective solutions. You are detail-oriented, balancing deep technical focus with a strategic view of project goals and timelines. Communication is one of your strengths—whether presenting simulation data, documenting design features, or collaborating across multidisciplinary teams, you articulate complex ideas clearly to both technical and non-technical audiences.

Beyond your technical expertise, you are committed to continuous learning and growth, staying abreast of industry trends and emerging technologies. You value diversity and inclusion, recognizing that great ideas come from a variety of perspectives. Your proactive and adaptable approach ensures you thrive in dynamic, innovative environments where your contributions drive meaningful impact.

What You’ll Be Doing:

• Reviewing SerDes standards to develop novel transceiver architectures and detailed sub-block specifications.
• Investigating and architecting circuit solutions that address performance bottlenecks, enabling significant improvements in power, area, and speed.
• Collaborating with cross-functional analog and digital design teams to streamline design and verification processes for optimal efficiency and quality.
• Overseeing and guiding the physical layout to minimize parasitics, device stress, and process variations, ensuring robust silicon performance.
• Presenting and reviewing simulation data with internal teams and external stakeholders, including industry panels and customer reviews.
• Documenting design features, test plans, and results, and consulting on electrical characterization and post-silicon analysis for product enhancements.
• Analyzing customer silicon data to identify design improvement opportunities and proposing solutions for post-silicon updates.
  
  

The Impact You Will Have:

• Drive innovation in high-speed analog/mixed-signal design, enabling next-generation connectivity solutions.
• Shape the architectural direction of SERDES IP, influencing industry standards and future product offerings.
• Enhance the performance, power efficiency, and reliability of Synopsys’ silicon IP portfolio.
• Mentor and elevate the technical capabilities of team members, fostering a culture of excellence and continuous learning.
• Directly contribute to successful customer deployments by addressing post-silicon challenges and ensuring robust field performance.
• Strengthen Synopsys’ market leadership in advanced process nodes and high-speed communication technologies.
  
  

What You’ll Need:

• MTech/MS with 4+ years or BTech/BS with 5+ years of practical analog IC design experience in Electrical or Computer Engineering (or related field).
• Proven expertise with FinFET technologies and CMOS tape-outs.
• Deep understanding of Multi-Gbps high-speed designs (PAM4, NRZ) and SERDES architectures.
• Extensive design experience with SERDES sub-circuits (e.g., TX, RX, adaptive equalizers, PLL, DLL, BGR, regulators, oscillators, ADC/DAC).
• Skilled in analog/digital co-design, calibration, adaptation, and timing handoff for optimized circuit performance.
• Familiarity with ESD protection, custom digital design, and design for reliability (EM, IR, aging, self-heating).
• Proficient with schematic entry, physical layout, design verification tools, and SPICE simulators.
• Experience with scripting languages (TCL, PERL, MATLAB) for post-processing simulation results.
• Understanding of system-level budgeting (jitter, amplitude, noise) and signal integrity (packaging, parasitics, crosstalk).
• Excellent communication and documentation skills.
  
  

Who You Are:

• Collaborative and open-minded, eager to share knowledge and learn from others.
• Detail-oriented and thorough, with a commitment to delivering high-quality results.
• Analytical thinker with strong problem-solving abilities and a proactive approach.
• Excellent communicator, able to convey complex technical concepts clearly.
• Adaptable and resilient in fast-paced, dynamic environments.
• Committed to fostering an inclusive, innovative, and supportive workplace.
  
  

The Team You’ll Be A Part Of:

You’ll join a world-class analog and mixed-signal R&D team at Synopsys, working alongside experts in high-speed IC design, verification, and CAD tool development. The team is collaborative, diverse, and passionate about innovation, with a focus on developing cutting-edge SERDES IP for advanced process nodes. You’ll have access to best-in-class design tools, mentorship, and opportunities for professional growth as you help shape the future of connectivity technology.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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