SOC IP Verification Engineer 

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SOC VERIFICATION

 

The Role

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.  

 

THE PERSON: 

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

 

Key Responsibilities

• Develop/Maintain tests for functional verification at SOC level.
• Build testbench components to support the next generation IP
• Maintain or improve current verification libraries to support SOC/Full-chip level verification
• Provide technical support to other teams
• Help Hardware emulation team to port the RTL to Palladium/Zebu or HAPS/Protium platforms.
  
  
  

• Strong Familiarity with Verification Methodologies such as OVM, UVM, or VMM
• Familiarity with Verilog and General Logic Design concepts
• Knowledge of system-level architecture including buses like AXI/AHB, bridges, memory controllers such as DDR4/DDR5, and peripherals such as USB, PCIe and Ethernet
• Knowledge of industry‑standard cryptographic and security algorithms (e.g., AES, RSA, SHA)
• Strong working knowledge of UNIX environment and scripting languages such as Perl or Python
• Excellent waveform debug skills using front end industry standard design tools like VCS, NCSIM/XCELIUM, Verdi, QUESTASIM
• Experience using UNIX Revision Control tools - ICM manage, CVS, Perforce and bug tracking tools such as JIRA
• Experience in verifying multimillion gate chip designs from specifications to tape-out
• Excellent communication and presentation skills
• Demonstrate the ability to work with cross-functional teams
• Familiarity with processors and boot flow would be useful
• Familiarity with Software development flow including assembly and C is beneficial
  
  
  

• BS/MS EE, CE, or CS
• 8+ years of design verification experience
• OOP coding experience (System Verilog, SpecmanE or C++) and SV Assertions