Senior Low Power Engineer Physical Design And PnR Flows

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

 

The Role

This position for a CAD Engineer will be critical to shaping the next generation AMD products, the leader in GPU, CPU. It requires interfacing with large design teams across the globe and owning development & support for next generation low-power place and route flows. Successful candidates would be responsible for automation of low-power PnR flows and methodologies for the 3nm & 2nm technology nodes as well as working closely with the EDA vendors to identify innovative solutions and track methodology issues.

 

 

THE PERSON: 

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems

 

KEY RESPONSIBILITIES: 

• Develop and maintain Power Grid (PG) construction and augmentation methodologies, including macro-PG tapping, PG EM/IR analysis and associated PG DRC closure
• Define and implement low‑power Place & Route flows supporting power gating and multi‑voltage domain designs
• Design and develop scripts and utilities to automate key components of the low‑power physical implementation flow
• Drive CAD low‑power flow and methodology development for advanced technology nodes, with preference for 3nm and 2nm process technologies
• Collaborate closely with synthesis, P&R, and signoff teams (STA, extraction, Physical Verification) to deliver best‑in‑class Power, Performance, and Area (PPA)
• Support global design teams on low‑power P&R and ECO implementations across multiple projects
  
  
  

• PREFERRED EXPERIENCE: 
• Extensive hands‑on experience with power gating and multi‑voltage design architectures.
• Strong understanding of low‑power implementation methodologies, including UPF, power gating, isolation strategies, level shifters, voltage areas, and power‑state tables.
• Proficiency in scripting and automation using Python, TCL, and Perl with strong debugging capabilities and CAD‑automation mindset.
• Expertise with industry‑standard physical design tools such as Synopsys Fusion Compiler and/or Cadence Innovus.
• Exposure to AI/ML concepts, with strong Python proficiency.
  

• Master’s/Bachelor’s Degree in Electronics Engineering (Minor in Computer Science preferred)
• 8-10 years of experience in CAD flow and methodology development on advanced nodes such as 3nm & 2nm
• Strong problem-solving skills and analytical thinking
• Team player, good work ethic, and excellent communication skills