Senior Functional Verification Engineer Graphics Multimedia

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

SMTS SILICON DESIGN ENGINEER

The Role

As a member of the Client/Graphics Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success.

The Person

A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

Key Responsiblities

• Responsible for participating in the pre-silicon verification for full chip, blocks, multi-chip and system-level verification
• Specifying design verification plan at soc level/IP level
• Specifying or reviewing verification plans for complex blocks within the ASIC
• Responsible for developing complex verification environment using the latest coverage/assertions based verification design methodology, which includes:
• self-checking, reusable, automated verification environment : both at full-chip & block level
• Constrained random generators and reference models
• Carve out the scope and work hands-on on functional verification.
  
  

• Minimum 12+ years of experience in ASIC Design Verification
• Must have excellent knowledge of ASIC Design Flow and SOC architecture
• Experience in developing complex testbench/model in verilog, System verilog or SystemC
• Experience with coverage-based verification methodology
• Experience in writing testplans and testcases
• Excellent debug skills in functional simulations are must.
• Experience in random test generation, coverage analysis, failure debug
• Experience in low power concepts/verification (NLP/UPF) and emulation is good-to-have
• Strong Verilog, SystemVerilog, PLI interface, C/C++, Perl/shell scripts programming skills.
• Must have very strong communication skills and the ability/desire to foster a team/global environment.
  
  
  

• Bachelors or Masters degree in computer engineering/Electrical Engineering