Senior Full Chip EM IR Analysis Engineer

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At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

  The Role

The focus of this role is to build, execute, and sign off on the Power and EMIR closure for the IP/Full chip SOC

THE PERSON: 

The candidate to have a passion for complex processor architecture, digital design, and verification in general. The candidate should be team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. The candidate should have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

 

KEY RESPONSIBILITIES: 

• EMIR closure at Tile /Partition/Subsytem/SOC levele on a particular node
• Drive Power and EMIR closure for design blocks and full-chip integration.
• Align EMIR analysis phases with PD milestones .
• Ensure compliance with signoff limits provided by SIPI team for given technology node
• Ability to analyze EMIR violations and propose implementation choices.
• Familiarity with DFx and scan architecture for EMIR considerations
• Technical Leadership
• Define EMIR signoff strategy, including IR drop and electromigration analysis.
• Review floorplan, clocking, and bus structures for IR hotspots.
• Coordinate bump allocation and power rail alignment with integration teams.
• Ownership of EMIR Flow & Signoff
• Collaboration & Coordination

• Work closely with block owners, PD team, and integration team to execute EMIR runs.
• Conduct EMIR run reviews and debug sessions with stakeholders.
• Methodology & Flow Development
• Maintain and improve EMIR flow
• Engage with SIPI team for current profile analysis and probe pad/interposer runs.
  

• Minimum 7 to 10 years of relevant work experience.
• Expertise in Synthesis , ICC2/ FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools.
• Expertise in Signoff tools like Redhawk_Sc, Voltas on EMIR, PT-PX for Power signoff and Primetime for Timing
• Should have worked as a go to person or technical lead for at least few full chip projects.
• Strong technical leadership and ability to mentor/guide/coach design engineers to achieve and deliver project goals.
• Strong inter-personal skills and ability to collaborate with teams spread across multiple geos.
• Should have good scripting experience in Shell, Python, Perl, TCL, UNIX along with decode/debug old existing scripts.
• Must be using AI technologies in day to day problem solving
  
  
  

• Bachelors or Masters degree in Electrical Engineering