Senior Analog Layout Engineer

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The Role

AMD is looking for a talented individual to join the Design Engineering team as a Staff Analog Layout Design Engineer in advanced process technology node 7nm and below. design high performance analog and digital circuits such as ADCs, DACs, PLLs, HBM, GDDR, DDR, LPDDR, References, Custom IOs, LDO, ESD which are integrated into AMD products

The Person

An experienced Analog Layout design engineer should be innovative, collaborative, meticulous, and curious.

Key Responsibilities

• Strong foundation in layout design for mixed analog / digital ICs with 7nm and below CMOS process geometries experience
• Experience in the layout of high performance data converters and / or high speed (GHz) circuit design would be an advantage
• Extensive Floorplanning, power grid and signal flow planning experience
• Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability
• Excellent understanding of signal and clock shielding and isolation techniques
• Excellent understanding of process non-idealities such as STI stress, well proximity effect and CMP effects and design strategies to mitigate these effects
• Excellent written and oral communication skills are also required
• Ability to work well as part of a team
• Excellent problem solving skills
• Strong foundation in layout design for mixed analog / digital ICs with 7nm and below CMOS process geometries experience
• Experience in the layout of high performance data converters and / or high speed (GHz) circuit design would be an advantage
• Extensive Floorplanning, power grid and signal flow planning experience
• Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability
• Excellent understanding of signal and clock shielding and isolation techniques
• Excellent understanding of process non-idealities such as STI stress, well proximity effect and CMP effects and design strategies to mitigate these effects
• Excellent written and oral communication skills are also required
• Ability to work well as part of a team
• Excellent problem solving skills
  
  
  

• Must have detailed knowledge of CMOS circuit theory.
• Must have ability to communicate with various teams to articulate specs and requirements as they pertain to layout
• Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools
• Must have at least 8 years of relevant or comparable experience doing analog layout design
• Knowledge of chip level integration and ESD concepts a plus
• Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability
• Good understanding of signal and clock shielding and isolation techniques
• Ability to work well as part of a team
  
  
  

• Bachelors or Masters degree in Electronics and Communication Engineering with 4+Yrs of exp