Low Power Design Engineer RTL

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.

AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.

The Role

The focus of this role is to plan, build, Design/Integration of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.  

 

THE PERSON: 

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

 

Key Responsibilities

• Define SoC and subsystem power architecture.
• Develop and maintain power intent using UPF/CPF methodologies.
• Implement low-power techniques such as:
• Power gating
• Clock gating
• Multi-voltage domains
• Dynamic Voltage and Frequency Scaling (DVFS)
• Retention and isolation strategies
• Collaborate with RTL designers to integrate low-power features.
• Run and debug low-power checks using EDA tools.
• Perform power estimation, analysis, and optimization throughout the design cycle.
• Drive power signoff activities and ensure compliance with project power budgets.
• Support functional verification teams in low-power verification planning and execution.
  
  

• Strong knowledge of digital IC/SoC design flow.
• Expertise in:
• UPF (Unified Power Format)
• CPF (Common Power Format)
• Power-aware simulation and verification
• Low-power design methodologies
• Experience with industry-standard EDA tools (Synopsys, Cadence, Siemens/Mentor).
• Understanding of RTL design (Verilog/SystemVerilog).
• Knowledge of static timing, synthesis, and implementation flows.
• Familiarity with power analysis tools and methodologies.
  
  

• Tcl
• Perl/Python
• Shell scripting
  
  
  

• Bachelors or Masters degree in computer engineering/Electrical Engineering