LEC CLP Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD.

At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future.

Whether you’re designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger — technology that moves the world forward. Join us and, together, we’ll advance your career.

MTS LEC and CLP SILICON DESIGN ENGINEER 

 

The Role

The focus of this role is to plan and execute the LEC and CLP of IP Subsystems and its signoff. This involves ownership of LEC and CLP at all physical partition level.

 

Key Responsibilities

• Responsible for LEC and CLP of all physical partitions of a device including its waivers, reviews and signoff
• Collaborate and support with design and/or implementation teams to achieve closure.
• Drive this activity with set of engineers by planning work and presenting regular status.
• Debug failure/issues and drive them to closure by working with CAD team or EDA vendor if required
  
  
  

• Highly Experienced in LEC and CLP with Synopsys or Cadence tool set.
• Complete Understanding of synthesis and Low power flows including UPF
• Have handled blocks with complex designs and their LEC/CLP lssues
• Have debug experience to solve issues.
• scripting and automation
  
  
  

• Bachelors with 6 years of experience or Masters degree with 4 year of experience in Electrical Engineering