Lead Verification Engineer - High Speed Protocol

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Lead Verification Engineer – Data Center Networking (AMD)

This is an exciting opportunity to join AMD’s Data Center Networking Technology Solutions group as a Lead Verification Engineer, contributing to next‑generation data center networking solutions that power AI training and inference at scale. In this role, you will lead verification for IP or subsystem or system‑level designs within high‑performance networking domains. You will collaborate closely with architects and designers while driving verification strategy, methodology, and execution.

Key Responsibilities

As a Lead RTL Verification Engineer, you will independently drive verification architecture, methodology, and execution for Data Center Networking IPs and systems:

Technical Responsibilities

• Work experience on high‑speed and complex protocols such as PCIe, Ethernet, CXL, RoCE / NVMe‑oF, etc.
• Architect, design, and develop testbench infrastructure and verification environments for complex networking IP and systems.
• Interpret product specifications and derive scalable and reusable verification architectures.
• Create comprehensive verification plans, test plans, coverage plans, and assertions.
• Build block‑level and multi‑block verification environments using System Verilog/UVM.
• Develop reusable verification components, sequences, and methodologies to ensure robust verification quality.
• Define and analyze coverage metrics, run regressions, debug failures, and manage overall regression health.
• Use scripting languages such as Python or Perl for automation and productivity improvements.
• Knowledge of AMBA protocols (AXI, APB) is an added advantage.
• Exposure to using AI‑assisted tools for verification productivity, debug acceleration, or test automation is a plus.
  
  
  

• Provide feedback during architectural discussions and influence verification approach early in the design cycle.
• Partner with cross‑functional teams including design, architecture, and validation.
• Support board‑level debug and validation efforts as needed.
• Mentor junior team members and drive best‑in‑class verification practices.
• Contribute to continuous improvement in verification methodologies and processes.
• Demonstrate strong ownership, accountability, and effective communication skills.
  
  
  

• Bachelor’s or master’s degree in EE/EC/CS.
• 7+ years of hands-on experience in IP/SoC/ASIC verification.
• Strong problem‑solving, analytical, and communication skills.