Lead Engineer CAD Digital Verification

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world’s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com.

The Role

In this role, you will develop, enhance, and support CAD tools and EDA simulation flows that enable efficient and reliable verification of Silicon Labs' semiconductor products. You will work on automation, simulation methodologies, and verification infrastructure to improve engineering productivity, design quality, and overall development efficiency.

This is a great opportunity for an experienced CAD or Design Verification Engineer who enjoys solving complex technical challenges, developing automation solutions, and working closely with design and verification teams to enable high-quality ASIC and SoC development.

Meet the Team

Our CAD – Digital Simulation team develops and maintains the tools, methodologies, and infrastructure that support digital simulation, design verification, formal verification, and low-power verification across Silicon Labs' engineering teams.

You will collaborate closely with RTL designers, Design Verification engineers, CAD teams, and EDA vendors to develop scalable verification solutions, improve simulation efficiency, and support advanced semiconductor design methodologies.

Responsibilities

As CAD Digital Verification Engineer, you will:

• Develop, deploy, and maintain CAD tools and EDA flows supporting Design Verification, Formal Verification, Low Power, Functional Safety, and Coverage Analysis.
• Work closely with RTL design and verification teams to understand technical requirements, identify challenges, and develop solutions that improve engineering productivity.
• Develop and optimize automation scripts using Python, Perl, Tcl, Bash, and shell scripting to streamline simulation builds, testbench generation, and verification workflows.
• Support ASIC/SoC simulation environments, including RTL simulation, gate-level simulation (GLS), and UVM-based verification flows.
• Collaborate with EDA vendors such as Cadence, Synopsys, and Siemens EDA to integrate new capabilities, debug tool issues, and resolve simulation bottlenecks.
• Support verification engineers in debugging complex simulation failures, analyzing functional and code coverage, and improving verification efficiency.
• Develop reusable and scalable CAD methodologies and automation solutions to improve verification quality and reduce turnaround time.
• Participate in technical discussions, project planning, and roadmap reviews while providing regular updates on tool enhancements and deployment activities.
  
  
  

• Bachelor's degree in Electrical Engineering, Electronics, Computer Engineering, or a related field with 7+ years of relevant industry experience, or a Master's degree with 5+ years of experience.
• Experience in Design Verification, CAD/EDA tool development, or verification flow support for ASIC/SoC designs. Strong understanding of IP/SoC-level verification methodologies and digital simulation environments.
• Hands-on programming and automation experience using Python, Perl, Tcl, C/C++, Makefiles, or shell scripting. Familiarity with RTL, Verilog/SystemVerilog, and UVM-based verification environments.
• Experience working with EDA simulation tools and verification workflows.
• Good understanding of Linux/UNIX environments, scripting, and engineering data-management workflows.
• Strong debugging, problem-solving, communication, and cross-functional collaboration skills.
  
  
  

• Experience with Cadence simulation and verification tools, including Cadence SYSVIP, SYSAPI, or SPA. Knowledge of low-power verification methodologies, UPF, and gate-level simulation (GLS).
• Experience with DPI integration using C/C++ for simulation and debugging.
• Exposure to formal verification, functional safety, and advanced coverage methodologies.
• Experience supporting or developing EDA flows using Cadence, Synopsys, or Siemens EDA tools.
• Demonstrated ability to debug complex EDA tool issues and collaborate with vendors to resolve technical challenges.
• Experience developing scalable automation frameworks and improving simulation performance across multiple engineering teams.
• Ability to work independently, manage technical priorities, and drive solutions in ambiguous or complex engineering environments.
  
  
  

• Equity Rewards (RSUs)
• Employee Stock Purchase Plan (ESPP)
• Insurance plans with Outpatient cover
• National Pension Scheme (NPS)
• Flexible work policy
• Childcare support