Layout Design Sr Engineer

Job Title: Analog/Mixed-Signal Layout Methodology Engineer

Company: Synopsys

Role Description:

Synopsys, at the forefront of technological innovation, is seeking an Analog/Mixed-Signal Layout Methodology Engineer. As a member of our Mixed Signal IP Methodology Team, you will work with the most advanced chip design technologies and tools. You will collaborate with local and global teams to develop capabilities that improve the time-to-market of complex mixed-signal designs in the latest technology nodes. This role offers the opportunity to lead technical projects, coordinate with other team members, and develop our best-in-class utilities.

Key Responsibilities:

• Propose and develop innovative methodologies to accelerate layout development without compromising quality.
• Collaborate with cross-teams in the enablement of advanced technology nodes.
• Measure project performance using appropriate systems, tools, and techniques.
• Establish and maintain relationships with cross-functional teams, internal and external customers.
• Create and maintain comprehensive methodology and workflow documentation.
  
  

• Familiarity with the physical design of analog and mixed-signal CMOS circuits.
• Proficiency in TCL and/or Python.
• Understanding of the full design cycle from RTL to GDSII, including chip level.
• Excellent communication skills.
• Strong organizational skills, attention to detail, and multi-tasking abilities.
• Experience with advanced FinFET nodes, TSMC 16 nanometer and below.
• Familiarity with Design tools such as Custom Compiler, Cadence Virtuoso, or equivalent.
• Knowledge of Verification tools like ICV, Calibre.
• Experience working with Jira/Atlassian or similar tools.
• Strong working knowledge of MS Office Suite of applications.
  
  

• MSEE or BSEE with a minimum of 3 years of related experience.
• Previous analog layout physical design experience.