ASIC Digital Design Staff Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent years verifying IP that has to work in silicon, not just pass regression. The difference between a clean tape-out and a respin often comes down to the corner case you caught at 2 AM in a Verdi waveform, and you are the engineer who finds it before it becomes a silicon bug. You read protocol specs the way some people read novels. UFS, UniPro, MIPI M-PHY are not just acronyms to you, they are systems you understand at the transaction level, the state machine level, and the timing level. You know where the edge cases hide.

Building a UVM environment from scratch does not intimidate you. Neither does inheriting someone else's testbench and making it better. You write sequences that stress the design in ways the spec did not explicitly call out because you have learned that is where the bugs live. Coverage closure is not a checkbox exercise for you, it is a conversation with the design about what actually matters.

You do not need someone to tell you what to verify next. You read the spec, talk to the designer, look at the waveform, and figure it out. At Synopsys, you will work on high-speed interconnect IP that powers real products, and what you verify will ship.

What You'll Be Doing

• Own end-to-end verification for MphyV6, UFS, and UniPro IP blocks, from test planning through coverage closure and sign-off
• Build and extend UVM testbenches in SystemVerilog, including agents, sequences, scoreboards, coverage models, and protocol checkers
• Write constrained-random and directed tests that expose corner cases, protocol violations, and timing edge conditions
• Debug complex failures using Verdi at the waveform, transaction, and protocol level, performing root-cause analysis on RTL and testbench issues
• Translate protocol specifications into executable test plans, SystemVerilog assertions, and functional coverage models
• Collaborate with design, architecture, and silicon validation teams on bug triage, ECO impact analysis, and tape-out readiness
• Mentor junior verification engineers through code reviews, debug sessions, and technical guidance on UVM best practices
  
  

The Impact You Will Have

• Catch silicon bugs before tape-out, directly reducing respin risk and time-to-market for high-speed interconnect IP used across the industry
• Deliver verified, production-quality IP blocks that meet protocol compliance and performance requirements for customer integrations
• Build reusable verification infrastructure that accelerates future IP development and improves regression quality across the team
• Drive coverage closure strategies that focus verification effort where it matters, not just where it is easy to measure
• Influence design decisions early by identifying architectural risks and edge cases during specification review
• Strengthen the technical capability of the verification team through mentorship, documentation, and knowledge transfer
• Contribute to first-silicon success by ensuring verification completeness and clear handoff to validation teams
  
  

What You'll Need

• Bachelor's with 5+ years or Master's with 3+ years in Electronics Engineering, Computer Engineering, or equivalent technical discipline
• Hands-on ASIC verification experience with ownership of IP or subsystem-level blocks
• Deep expertise in UVM methodology and SystemVerilog, including testbench architecture, constrained-random verification, and coverage-driven verification
• Strong working knowledge of high-speed protocol standards such as UFS, UniPro, MIPI M-PHY, PCiE, or similar interconnect protocols
• Proficiency with Verdi for waveform debug, transaction-level analysis, and protocol visualization
• Experience writing SystemVerilog assertions and building functional and code coverage models
• Demonstrated ability to work independently, drive verification closure, and communicate technical issues clearly across teams
  
  

Who You Are

• You can look at a failing regression, open Verdi, and within an hour tell the team whether it is an RTL bug, a testbench race, or a protocol misunderstanding
• You push back when a test plan is too vague or a coverage metric does not actually measure the risk it claims to address
• Ambiguity does not stop you. When the spec is unclear or the design is still evolving, you make reasonable assumptions, document them, and keep moving
• You explain complex protocol behavior to designers and architects in a way that gets to the issue without requiring them to read 200 pages of specification
• Mentoring junior engineers is not a distraction for you. You see it as part of building a team that can verify harder problems faster
• You care about the quality of your testbench code as much as you care about the quality of the RTL you are verifying
  
  

The Team You'll Be Part Of

Your recruiter will share more about the team structure and mission during the interview process.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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