ASIC Design Verification Engineer

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ASIC DESIGN VERIFICATION ENGINEER 

 

The Role

Adaptive and Embedded Computing Group (AECG) seeks a Staff Silicon Design Verification Engineer to provide technical leadership and expertise in the verification of high-speed Crypto, Network-on-Chip (NoC), and cutting-edge DRAM Memory Controller IPs (LPDDR6, HBM4). You will be responsible for architecting, developing, and utilizing simulation and/or formal-based verification environments at both block and SoC-level to achieve first-pass silicon success.

The Person

The ideal candidate has a proven track record in driving strategies and successfully executing verification strategies for Pre-Silicon Design IP and/or SOC designs. They should be strong team players with excellent communication and leadership skills, capable of positively and strategically influencing design teams to improve overall product quality.

Key Responsibilities

• Lead the verification of high-speed Crypto, Network-on-Chip (NoC), cutting-edge DRAM Memory controller (LPDDR6, HBM4) designs, ensuring the highest standards of quality and performance.
• Architect, develop, and use simulation and/or formal-based verification environments at IP and SoC-level.
• Lead and manage verification teams, including planning, execution, tracking, verification closure, and delivery to programs.
• Develop and execute comprehensive verification plans, including testbenches and test cases.
• Collaborate with design, architecture, and software teams to define and implement verification strategies.
• Utilize advanced verification methodologies, including UVM, formal verification, and assertion-based verification.
• Mentor and guide junior engineers, fostering a collaborative and innovative team environment.
  
  
  

• Require proven track record in technical leadership of teams with 5+ engineers. This includes planning, execution, tracking, verification closure, and delivery to programs.
• Require experience with development of UVM and System Verilog test benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium.
• Require strong understanding of state of the art of verification techniques, including assertion and metric-driven verification. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high-performance IP and/or VLSI designs is a plus.
• Require familiarity with verification management tools as well as an understanding of database management particularly as it pertains to regression management.
• Experience with formal property checking tools such as VC Formal (Synopsys), JasperGold (Cadence), and Questa Formal (Mentor) is a plus.
• Experience with gate-level simulation, power-aware verification is a plus.
• Experience with silicon debug at the tester and board level, is a plus.
  
  
  

• Require BS w/ 8+ yrs or MS w/ 6+ yrs or PhD w/ 3+ yrs in Electrical Engineering, Computer Engineering or Computer Science.