Design Verification Engineer

This role is for one of Weekday’s clients

Min Experience: 4+ years
Location: Hyderabad
JobType: full-time

We are looking for an experienced Design Verification Engineer with 4–8 years of industry experience to join our hardware verification team. The ideal candidate will have strong expertise in digital design verification, with hands-on experience in SystemVerilog (SV) and Universal Verification Methodology (UVM). Exposure to high-speed protocols such as PCI Express (PCIe) will be highly valued.

You will be responsible for developing robust verification environments, creating comprehensive test strategies, identifying functional issues, and ensuring that complex IPs and SoCs meet their design and performance requirements.

• Develop and maintain scalable and reusable verification environments using SystemVerilog and UVM.
• Create verification plans, test scenarios, test cases, and functional coverage models based on design specifications.
• Develop and integrate UVM components including agents, drivers, monitors, sequencers, scoreboards, and reference models.
• Write and maintain SystemVerilog-based constrained-random and directed tests.
• Develop assertions and coverage mechanisms to improve verification quality and identify corner-case scenarios.
• Perform functional, integration, and regression testing across different design configurations.
• Debug simulation failures, analyze waveforms, identify root causes, and work closely with RTL designers to resolve issues.
• Build and maintain verification infrastructure for complex digital IPs and SoC subsystems.
• Monitor functional and code coverage and drive verification closure through systematic analysis.
• Collaborate with RTL, architecture, firmware, and validation teams throughout the product development lifecycle.
• Contribute to improving verification methodologies, automation, reusable testbenches, and regression processes.
• Participate in design and verification reviews and provide technical inputs on testability and verification strategies.

• 4–8 years of experience in ASIC, SoC, IP, or semiconductor design verification.
• Strong understanding of digital design concepts and hardware verification methodologies.
• Hands-on programming experience with SystemVerilog (SV).
• Strong practical knowledge of UVM and object-oriented verification concepts.
• Experience developing reusable and modular UVM-based testbenches.
• Good understanding of simulation, debugging, functional coverage, code coverage, and regression methodologies.
• Experience with industry-standard simulation and verification tools such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.
• Ability to interpret RTL, specifications, protocols, and verification requirements.
• Strong debugging, analytical, and problem-solving skills.
• Good understanding of ASIC/SoC development and verification flows.

• Hands-on experience with PCIe verification, preferably across different PCIe generations.
• Understanding of PCIe protocol architecture, transaction layer, data link layer, physical layer, configuration space, and enumeration.
• Experience verifying PCIe controllers, endpoints, root complexes, switches, or related IP.
• Familiarity with PCIe VIPs and protocol-level debugging.
• Experience developing protocol-specific UVM environments and scoreboards.
• Knowledge of SystemVerilog Assertions (SVA) and advanced coverage techniques.
• Exposure to scripting languages such as Python, Perl, or Tcl for verification automation.
• Experience with formal verification or emulation is an added advantage.
• Familiarity with other high-speed or industry-standard protocols is a plus.