Analog Layout Engineer

About the Role

Cyient Semiconductor is looking for highly motivated and skilled Analog Layout Engineers with strong experience in Non-FinFET technologies to join our growing Analog & Mixed-Signal design team. The ideal candidate should possess hands-on expertise in custom analog layout development, physical verification, and layout optimization for advanced analog and mixed-signal IPs.

Key Responsibilities

• Develop high-quality custom analog layouts for blocks such as:
  • Bandgap References
  • LDOs
  • Charge Pumps
  • PLLs
  • Data Converters (ADC/DAC)
  • Current Mirrors
  • Op-Amps
  • Comparators
  • PMIC Blocks
• Perform floorplanning and layout implementation while ensuring optimal matching, symmetry, noise isolation, and reliability.
• Execute and debug physical verification checks including:
  • DRC
  • LVS
  • ERC
  • Antenna Checks
  • Density Checks
• Collaborate closely with circuit designers to achieve performance, area, and power targets.
• Understand parasitic effects and work on extraction-related layout improvements.
• Implement layout techniques such as:
  • Common Centroid
  • Interdigitation
  • Shielding
  • Guard Rings
  • Device Matching
  • ESD-Aware Layout Practices
• Support tape-out activities and resolve foundry sign-off issues.
• Work with cross-functional teams to ensure successful project execution.

Required Skills & Experience

Technical Skills

• 3-5 years of hands-on experience in Analog Layout Design.
• Strong experience in Non-FinFET process technologies such as:
  • 180nm
  • 130nm
  • 90nm
  • 65nm
  • 40nm
• Experience in Analog/Mixed Signal layouts and PMIC layouts.
• Strong understanding of:
  • Matching techniques
  • Noise coupling
  • Electromigration
  • Latch-up prevention
  • ESD concepts
• Hands-on experience with:
  • Cadence Virtuoso Layout Suite
  • Calibre DRC/LVS
  • Parasitic Extraction Tools
• Good understanding of semiconductor fabrication processes and device structures.

Preferred Qualifications

• Experience in PMIC, Automotive, Industrial, Consumer Electronics, or Power Management products.
• Exposure to complete chip tape-out cycle.
• Knowledge of reliability and yield optimization techniques.
• Experience working with TSMC, GlobalFoundries, UMC, or similar foundry technologies.

Educational Qualification

• B.E./B.Tech/M.E./M.Tech in Electronics, VLSI, Microelectronics, Electrical Engineering, or related field.