Staff Engineer Design Verification CPU Cluster

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Were looking for a passionate and hands-on RISC-V CPU Cluster Design Verification Engineer to architect, develop, and evolve world-class verification infrastructure for high-performance RISC-V cores and clusters. If building from scratch, innovating on methodology, and collaborating with top-tier CPU designers excites you — read on.

This role is hybrid, based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting

Who You Are

• The kind of engineer who can take ownership of verification from day one — building environments in SystemVerilog, UVM, and C++ comes naturally.
• Thinks at the system level, with experience bringing together multiple IPs and making sure they play well together.
• Knows how to plan stimulus, track down bugs, and close coverage for complex subsystems like caches, NoCs, and memory.
• Ready to tackle tricky cross-IP features like coherence and security, and ensure they work reliably at the SoC level.
  
  

• A background in Electrical Engineering, Computer Science, or a similar field — Bachelor’s or Master’s level.
• Real experience working with SystemVerilog and UVM to verify complex designs.
• Someone who’s led DV efforts at the subsystem or SoC level, from integration through validation.
• Comfort with multi-IP verification flows and familiarity with protocols like AXI or CHI, plus system IPs like debug and power management.
  
  

• How to scale DV infrastructure for high-performance RISC-V clusters and SoCs.
• Verification strategies for multi-agent systems across CPUs, IPs, and interconnects.
• Best practices for integration-level planning and cross-IP feature convergence.
• Collaborating across RTL, DV, software, and validation teams to drive system-level bring-up.