Sr Staff Engineer Post-Silicon Validation

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are looking for a Post-Silicon Validation Engineer to drive bring-up, validation, and debug of RISC-V–based SoCs. This role sits at the intersection of silicon, firmware, and system software, and requires hands-on lab experience and understanding of SoC architectures.

You will own post-silicon validation from first-silicon bring-up through production readiness, working closely with design, pre-silicon verification, firmware, and software teams.

This role is hybrid , based out of Bangalore.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• You are a seasoned post-silicon engineer with 10+ years of experience in SoC bring-up, validation, and silicon debug.
• You have a strong grasp of CPU and SoC architectures, including RISC-V privilege modes, caches, coherency, and memory systems.
• You are comfortable debugging complex hardware/software interaction issues using lab tools and low-level software.
• You thrive in cross-functional environments and enjoy working closely with RTL, firmware, and software teams to solve hard problems.
  
  

• Lead first-silicon bring-up of RISC-V CPU–based SoCs and execute post-silicon validation plans.
• Debug silicon issues across CPU cores, interconnects, memory subsystems, peripherals, and high-speed interfaces.
• Develop and debug bare-metal tests, boot flows, and collaborate on Linux bring-up and driver validation.
• Provide actionable feedback, support ECO validation, and drive fixes for future silicon revisions.
  
  

• Deep hands-on exposure to cutting-edge RISC-V SoCs, AI accelerators, and high-performance compute platforms.
• End-to-end ownership across the silicon lifecycle—from first silicon to stable production.
• Advanced silicon debug techniques spanning hardware, firmware, and operating systems.
• Opportunities to influence architecture, validation strategy, and future silicon direction in a highly visible role.