RTL Design Engineer Google Cloud

Minimum qualifications:

• Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science or a related field, or equivalent practical experience.
• 4 years of experience in ASIC development with Verilog/SystemVerilog, very high speed integrated circuit (VHSIC), hardware description language (VHDL), or Chisel.
• Experience with micro-architecture and designing IPs and subsystems.
• Experience in ASIC design verification, synthesis, timing/power analysis, and design for testing (DFT).
  
  

Preferred qualifications:

• Experience with coding languages (e.g., Python or Perl).
• Experience in System on a Chip (SoC) designs and integration flows.
• Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
• Knowledge of high performance and low power design techniques.
  
  

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Googles direct-to-consumer products. Youll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will be part of a team developing Application-specific integrated circuit (ASICs) used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design to specify and deliver quality designs for next generation data center accelerators. You will solve technical problems with micro-architecture and practical reasoning solutions, and evaluate design options with complexity, performance, power.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

• Own microarchitecture and implementation of internet protocol (IP) and subsystems.
• Work with Architecture, Firmware, and Software teams to drive feature closure and develop micro-architecture specifications.
• Drive design methodology, libraries, debug, code review in coordination with other IP design verification (DV) teams and physical design teams.
• Identify and drive power, performance and area of improvements.
  
  
  

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Googles EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

---