Applications Engineering Sr Staff Engineer

About Synopsys:

At Synopsys, we are at the heart of driving innovations transforming the way we live and work. We are now living in era of ‘Smart Everything’ encompassing the integration of advance technologies like robotics, autonomous cars, artificial intelligence, the cloud, 5G, and the Internet of Things (IoT) around us. We deliver the world’s most advanced EDA Tools and Intellectual Properties(IPs) for advance node chip designing empowering the continued development of these breakthrough technologies. If you share our passion for innovation, we are delighted to offer you exciting opportunities to become part of our grand journey of passing our innovative technologies in shaping future of mankind.

Business Area Description:

Our Electronic Design Automation (EDA) business focuses on creating state-of-the-art tools and solutions for designing highly complex and advanced AI-driven silicon chips. These next-generation chips are designed to handle higher data capacities, operate at gigahertz-plus speeds, and consume minimal power. As the world’s leading provider of EDA solutions, we collaborate with semiconductor ecosystem partners to co-develop process and design methodologies, accelerating chip manufacturing success. We enable our customers to optimize chips for power, cost, and performance, significantly reducing their project timelines.

Job Summary:

We are seeking a Physical Design Specialist for the role of Senior Staff Application Engineer. In this role, you will collaborate with leading-edge customers on advanced nodes (sub-2/3nm), developing AI-driven RTL-to-GDS methodologies using Synopsys tools like Fusion Compiler and DSO.ai. Your goal will be to achieve the best-in-class PPA with improved cycle time execution.

Key Responsibilities:

• Partner with leading customers to develop and implement advanced AI-driven RTL-to-GDS methodologies using Synopsys EDA tools, IPs and libraries.
• Create and optimize flows and solutions to meet PPA requirements for high-frequency cores, automotive designs, and high-capacity AI and compute designs.
• Enable the deployment of flows/solution utilizing Synopsys tools like Fusion Compiler, RTL Architect, and AI-based Design Space Optimization engines, along with Tcl/Python scripting.
• Co-publish innovative work and methodologies with partnering customers in international technical conferences.
• Collaborate with the R&D team to share customer requirements and define product specifications for new feature development.
• Demonstrate Synopsys tools and technologies to customers, provide training, and offer technical support.
• Manage multiple customer engagements and technical evaluations, working closely with the account management team.
• Develop new business campaigns and strategies for expanding Synopsys user segments and verticals.
• Lead and mentor a team of junior application engineers, providing technical guidance and managing project tasks.
  
  

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or in related field.
• 10+ years of experience in ASIC design using Synopsys Implementation or industry-standard tools, with a focus on Placement, Optimization, CTS, and Routing.
• Comprehensive RTL-to-GDSII flow knowledge and hands-on experience with backend P&R tools (e.g., Fusion Compiler/ICC2). Good experience of physical synthesis, timing closure, CTS, macro placement, routing at advanced nodes and timing closure.
• Strong understanding of advanced node design methodologies and design timing/power constraints.
• Proficient in Tcl/Python scripting.
• Excellent verbal/written communication and presentation skills.
• Ability to manage multiple priorities and effectively address customer challenges.
• Experience in technical account management and team leadership.
  
  

• Familiarity with frontend synthesis tools (Fusion Compiler/Design Compiler), STA (PrimeTime), and physical verification (ICV or similar tools).
• Technical account management, Customer Handling and Training