Static Timing Methodology Development For Gate Level Timing Signoff

Introduction

About IBM

IBM’s greatest invention is the IBMer. We believe that progress is made through progressive thinking, progressive leadership, progressive policy and progressive action. IBMers believe that the application of intelligence, reason and science can improve business, society and the human condition. Restlessly reinventing since 1911, we are the largest technology and consulting employer in the world, with more than 380,000 IBMers serving clients in 170 countries.

About Business Unit

India Systems Development Lab (ISDL) is part of IBM Systems world-wide technology development lab. Established in 1996, the Lab is headquartered in Indias Silicon Valley and startup hub - Bengaluru, with a strong presence in Pune and Hyderabad. Developers at ISDL deliver technology innovations across the entire Systems portfolio - z Systems, Power / OpenPOWER Systems and Storage. The team here works across the entire stack from processor design, firmware, operating system to software defined storage. The lab also focuses on innovations, thanks to the creative energies of the teams. The lab has contributed over 400+ patents in cutting edge technologies and inventions so far.

We are part of Einstimer (industry leading Static timing Analysis tool) Development team under Electronic Design Automation (EDA) organization, and responsible for timing analysis of high performance hardware design for IBMs next generation Systems (IBM P and Z Systems) which is used in Cognitive, ML, DL, and Data Center applications.

Your Role And Responsibilities

Your Role and Responsibilities :

We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering & Electronics & Communication Engineering ready to handle the challenging problems in future technologies and designs.

We are also looking for candidates with Machine Learning/AI and/or Data Science background to lead our leading-edge algorithms and AI technology within our EDA solutions to increase our design team’s productivity and chip quality and performance.

Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world.

We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team.

Strong interpersonal skills are needed to coordinate deliverables and requirements from several areas within and outside of the organization. There are many opportunities to gain and utilize a deep understanding of future issues and provide input towards decisions affecting system development, logical and physical design as well as sophisticated methodology directions.

Individuals who are chosen to become a part of our world class development teams will be helping advance IBM’s leadership in developing the highest performing computers and changing hardware solutions. Do you want to be an IBMer? Come THINK with us!

Preferred Education

Masters Degree

Required Technical And Professional Expertise

• Individual contributor for Gate Level Sign off Timing team to work on ASICs or Server Timing Methodology.
• 5-8 years of hands on experience with Static Timing Analysis
• Hands on experience with Cadence Tempus tool or Synopsys Primetime
• EDA Tool/Methodology development experience
• Thorough understanding of Static Timing Analysis. Knowledge of other VLSI domains is a plus
• Proven problem-solving skills and the ability to work in a team environment are a must
• Excellent scripting skills - TCL/Python/Shell