Staff Engineer - Verification

Candidate should have strong background in digital verification to develop advanced test benches using System Verilog and UVM.

Your Role

Key responsibilities in your new role

• Candidate should have strong background in digital verification to develop advanced test benches using System Verilog and UVM.
• Should have developed multiple verification environments for complex IP’s and SoC’s by defining new architecture.
• Having knowledge in SoC verification covering RTL, Power Aware and Gate level simulations is preferable.
• Exposure to deployment of automation methods and formal verification methodologists preferable.
• Define and implement verification concepts for complex SoCs usingstate-of-the-art methodologies such metric driven, formal and emulation-based verification.
• Co-ordinate the overall verification strategy.
• Define and control verification management activities such as verification planning, verification tracking and reporting.
• Control for work process compliance and high-quality verification sign-off.
  
  

Your Profile

Qualifications And Skills To Help You Succeed

• Bachelors/Masters in Electrical/Electronics Engineering with 8+ years of experience in Advanced user of System Verilog & UVM for IP , Subsystem, SOC level verification.
• Exposed to Coverage Driven & Constraint random Verification
• Experience with Assertion based & Formal Verification.
• Experience with low power design aspects , Power Aware Verification(UPF) and Gate level.
• Experience in verification of designs in RTL & GLS.
• Experience in developing verification architecture.
• Experience in leading a team, create & execute test plan, Coverageclosure
  
  

Contact:

Shavin.Shashidhar@infineon.com

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