Staff Engineer Design

Your Role

Key responsibilities in your new role

• Setup platform for SoC verification and work closely with team members to review and understand the relevant functional requirements
• Write automation scripts to meet these requirements after close alignment with other verification teams for proper work split according to mutually acceptable verification assignment
• Good understanding on verification plan by developing C/C++ test cases and System Verilog/UVM test bench components and by integrating 3rd party VIP components
• Initially in project Design Application Engineer would be responsible to simulate, sanity of source code, Unit Delay, and Gate Level using appropriate tools and flows including Emulator, Portable Stimulus, or Formal methodologies for functional and toggle coverage closure.
• Lead a team technically through exploring new environment and identifying potential enhancement areas through new methodology
• Identify and setting mid/long term goals based on bench marking against industry standards
  
  

Your Profile

Qualifications And Skills To Help You Succeed

• Masters/Bachelors in VLSI/Electronics & communication Engineering with 6+ years of relevant work experience.
• Strong foundational knowledge of digital design & verification.
• Advanced knowledge and hands-on experience of System Verilog and UVM.
• Hands-on experience in hardware-software debugging at the system or application level. Hand-on experience with gate-level-simulations and with debugging/troubleshooting skills is a plus
• Exposure to version-controlling (eg, Git/Bitbucket, ClearCase, CVS,SVN) and bug-management schemes
• Dynamic and energetic with zero verification escape mindset
• Self-motivated, flexible, good communication with interpersonal skills and is a good team player who is able to work well with both internal and external partners.
• Candidate has proven ability to achieve results in a very dynamic, multi-site environment and be able to coordinate with priorities and self-initiatives.
• Application engineering profile with Verification setup in High and Low Speed COM, CPU peripherals, BUS or pattern development. Experience in test bench/verification environment set up is also a plus.
• Candidate who has more relevant working experience will be considered for challenging assignments.
  
  

Contact:

Gowri.Shenoy

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