Principal Compilers Engineer

Job Description

We're looking for a Principal Compiler Engineer to own the system software stack that sits between Anthriq Silicon and the applications running on it, compiler infrastructure, low-level firmware, and real-time signal compute pipelines with sub-millisecond latency requirements. The ideal candidate has shipped production LLVM compiler pipelines at a semiconductor company, has hands-on embedded bring-up experience, and brings formal verification rigour to safety-critical real-time systems. Responsibilities: - Own custom LLVM backend passes, instruction selection (SelectionDAG / GlobalISel), MIR-level optimisations, and register allocator improvements for real-time execution paths. - Build compiler fuzzing infrastructure and formal verification frameworks (Alive2 / SMT), with zero miscompilations in safety-critical pipelines. - Implement device drivers and protocol stacks (USB, SPI, I2C, UART, PCIe, CAN) for real-time biosignal acquisition. - Work with Linux kernel subsystems, RT-PREEMPT, SCHED_FIFO, and kernel modules for deterministic biosignal scheduling. - Profile and optimise across CPU / GPU architectures using perf, gdb, Nsight, rocprof, valgrind, and eBPF. - Author SRDs and SDDs; lead design reviews and mentor engineers across C++, LLVM, and embedded systems. - Collaborate with hardware teams on silicon bring-up and BSP development ahead of tape-out. Requirements: - 12+ years in system-level C++ spanning GPU compiler engineering, embedded firmware, and kernel-adjacent work. - Deep LLVM expertise: SelectionDAG, GlobalISel, MIR, register allocator, TableGen, custom pass development. - Embedded Linux / RTOS (FreeRTOS, Zephyr) with hard real-time constraints; firmware bring-up across SPI / I2C / USB / PCIe / eMMC. - GPU programming: CUDA / HIP; GPU execution model expertise (warp scheduling, register files, occupancy). - Compiler correctness: fuzzing harnesses, formal verification (Alive2 SMT/SAT), differential testing. - Advanced debugging: gdb, Lauterbach JTAG, logic/protocol analysers, AddressSanitizer. Good to have: - FPGA design (Verilog / VHDL) and assembly-level programming (PTX, GCN, SASS, x86 8051). - DSP fundamentals or biosignal pipeline experience (EEG, EMG). Company Summary Anthriq builds the foundational infrastructure for human-aware technology. Our infrastructure serves as the Human Body API, a comprehensive gateway to capture, decode, and interpret electrophysiological signals from the human body. Through years of development, we've created a modular, Lego-like technology that enables our customers to move from signal capture to deployment without reinventing the stack. Our integrated system transforms biosignals, brain activity, muscle movements, and physiological responses into real-time, programmable applications. Our research focuses on two critical areas: developing fundamental frameworks that standardize biosignal intelligence and building the world's most comprehensive biosignal data repository. This dual approach ensures that human biological signals can be as easily integrated into technology as any other data source. At Anthriq, we're enabling a future where technology responds to human intent, not interfaces. Why Join Us As a team of young seekers, we are building technology for tomorrow while creating a workplace we love. Inspired by each other, we've crafted a flexible work-life philosophy that suits our dynamic lifestyle and embodies the true spirit of an organization for the future.

Required Skills

['Compilers', 'LLVM', 'C++', 'RTL', 'FPGA', 'Verilog', 'Firmware Development', 'Embedded Systems', 'RTOS', 'UART', 'SPI', 'I2C']

Additional Information

NA