Staff Engineer - Physical Design And Signoff Synthesis To GDS2

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an experienced, self-motivated engineering professional with a deep-rooted passion for semiconductor technology and innovation. Your technical expertise spans Physical Design, Physical Verification, and Static Timing Analysis (STA) at the IP/block/full chip level, and you are adept at navigating the complexities of advanced Finfet and GAA process technologies. You thrive in fast-paced, collaborative environments, drawing energy from teamwork and cross-functional problem-solving. You have a strong analytical mindset, coupled with a keen eye for detail, enabling you to deliver robust, high-quality solutions that meet stringent performance and reliability requirements. Your communication skills empower you to clearly articulate technical concepts and collaborate effectively with both local and global teams, as well as external customers. You are proactive, always seeking new ways to improve methodologies and processes, and you are committed to continuous learning and professional growth. Your dedication to excellence and innovation drives you to contribute meaningfully to the development of industry-leading products. If you are eager to work at the cutting edge of chip design and play a pivotal role in shaping the next generation of silicon technologies, Synopsys is the place for you.

What You’ll Be Doing:

• Conceptualizing, designing, and productizing state-of-the-art RTL to GDS implementation for SLM monitors using ASIC design flows.
• Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for silicon biometrics and reliability.
• Executing digital backend activities, including synthesis, pre-layout STA, SDC constraints development, floor planning, bump placement, power planning, MV design techniques, VCLP, UPF understanding, placement, CTS, and routing.
• Driving post-layout STA, timing and functional ECO development, and timing signoff methodology for high-frequency IP design closure.
• Performing physical verification tasks such as DRC, LVS, PERC, ERC, Antenna, EMIR, and Power signoff.
• Collaborating with architects and circuit design engineering teams to create and refine new flows and methodologies.
• Ensuring pre-layout and post-layout timing closure and timing model characterizations across various design corners, meeting reliability and aging requirements for automotive and consumer products.
  
  

The Impact You Will Have:

• Accelerating the integration of next-generation intelligent in-chip sensors and analytics into Synopsys technology products.
• Optimizing performance, power, area, schedule, and yield at every stage of the semiconductor lifecycle.
• Enhancing product reliability and differentiation in the market, reducing risk for customers and partners.
• Driving innovation in physical design, verification, STA, and signoff methodologies and tools.
• Contributing to industry-leading SLM monitors and silicon biometrics solutions that set new standards.
• Collaborating with cross-functional teams to ensure successful deployment and adoption of advanced technologies.
  
  

What You’ll Need:

• BS/B.Tech or MS/M.Tech in Electrical Engineering with 5+ years of relevant industry experience.
• Strong knowledge and hands-on experience in Physical Design, Physical Verification, pre- & post-layout STA, and EMIR/Power signoff, including SDC development and UPF/Multivoltage design.
• Mandatory experience with DRC, LVS, DFM cleaning, and timing closure.
• Proficiency in digital design tools from any EDA vendor, preferably Synopsys tools (FC/VCLP/PT/PT-PX/ICV/Redhawk).
• Sound understanding of Physical Design, Physical Verification, STA, and signoff concepts, with proven track record in generating ECO for DRV cleaning and timing closure.
• Experience with advanced nodes (14nm, 10nm, 7nm, 5nm, 3nm, 2nm) and successful tape-outs.
• Good understanding of OCV, POCV, derates, crosstalk, and design margins.
• Experience in scripting (TCL/PERL) for custom methodologies and flow enhancements.
  
  

Who You Are:

• Proactive and detail-oriented with excellent problem-solving skills.
• Adept at working independently and providing innovative physical design and signoff solutions.
• Excellent communicator and team player, capable of collaborating effectively with diverse teams.
• Innovative thinker with a passion for technology and continuous improvement.
• Committed to delivering high-quality results and achieving ambitious project goals.
  
  

The Team You’ll Be A Part Of:

You’ll join a dynamic, collaborative team of engineering professionals focused on advancing the state-of-the-art in chip design and verification. The team works closely with architects, circuit designers, and cross-functional partners to deliver innovative solutions for semiconductor lifecycle monitoring, reliability, and performance. With a culture of continuous learning and knowledge sharing, you’ll be empowered to contribute ideas and play a key role in shaping the future of Synopsys technology.

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