Silicon Engineer Design Verification

Minimum qualifications:

• Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 1 year of experience with creating/using verification components and environments in UVM methodology at IP or Subsystem level.
• Experience developing and maintaining design verification (DV) testbenches, test cases, and test environments.

Preferred qualifications:

• Masters degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with image processing, computer vision or machine learning IPs.
• Experience with AMBA (APB/AXI/ACE) or other standard protocols.
• Familiarity with CPU, GPU or other computer architectures.

About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Googles direct-to-consumer products. Youll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The Platforms and Devices team encompasses Googles various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our users interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities:

• Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use.
  
• Plan the verification of digital design blocks by understanding design specifications and collaborating with design engineers to identify key verification scenarios.
• Create and improve constrained-random verification environments using SystemVerilog and UVM. Optionally use SystemVerilog Assertions (SVA) and formal tools for formal verification.
• Perform power-aware simulations and formal verification to validate power management features like clock gating, power gating, and DVFS. Develop and implement power-aware test cases, including stress and corner-case scenarios, for power integrity.
• Develop and execute coverage-driven verification plans to ensure comprehensive coverage of ASIC designs. Collaborate with design engineers to resolve coverage issues and improve design quality.