Silicon DFT Engineer

Minimum qualifications:

• Bachelors degree in Electrical Engineering or a related field, or equivalent practical experience.
• 2 years of experience with analog or mixed-signal Integrated Circuit (IC) design.
• Experience with system-on-chip design/integration flow, and design automation.
• Experience with Design for Test (DFT) technologies such as Scan, Algorithmic Test Pattern Generation (ATPG) and Memory Built in Self Test (MBIST).
• Experience with Application-Specific Integrated Circuit (ASIC) DFT synthesis, STA, simulation, and verification flow.

Preferred qualifications:

• Masters degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
• Experience working with Automatic Test Equipment (ATE) engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.).
• Experience in System on a Chip (SoC) cycles, including silicon bring-up and silicon debug activities.
• Experience in fault modeling.

About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Googles direct-to-consumer products. Youll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Were the driving force behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities:

• Document Design for Testability (DFT) architecture and test sequences, including boot-up sequence associated with test pins.
• Participate in DFT logic insertion like scan and BIST at Register-Transfer Level (RTL) and netlist level.
• Perform DFT checks for scan coverage and memory Built-In Self Test (BIST).
• Plan SoC/IP/Subsystems (SS) DFT and collaborate with cross-functional teams, DFT constraints development for timing closure and Physical Design (PD)/Static Timing Analysis (STA) support.
• Perform quality check flows like Lint, Clock Domain Crossing (CDC) of the DFT RTL in DFT modes. Participate in design debug, code review in coordination with other IPs Design Verification (DV) teams and Physical Design teams.

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