Senior AI ML Hardware Architect Google Cloud

Minimum qualifications:

• Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in architecture and micro-architecture design of graphics or Machine Learning (ML) or Ethernet/ROCE/UAL/NVlink scaleup/out fabrics or managing Low Precision/Mixed Precision Numerics/Vector processors/DSP processors or experience architecting networking ASICs.
• Experience in memory hierarchy on chip fabrics, memory controllers, High Bandwidth Memory (HBM), and Dynamic Random-Access Memory (DRAM) technologies.

Preferred qualifications:

• Masters degree or PhD in Computer Engineering, Electrical Engineering, or equivalent practical experience.
• Experience working with software teams optimizing the hardware/software interface.
• Experience in performance analysis and modeling, defining and driving performance test plans.
• Experience in programming languages (e.g., C++, Python).
• Knowledge of arithmetic units, bus architectures, accelerators or memory hierarchies and high performance and low power design techniques and use of ML tools for building smarter tools.

About the job:

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Googles most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Googles TPU. Youll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Googles most demanding AI/ML applications. You will be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Googles TPU. You will contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

Were the driving force behind Googles groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities:

• Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and evaluate quantitative and qualitative performance and power analysis.
• Own microarchitecture of compute blocks and subsystems and partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces.
• Evaluate different silicon solutions for executing Google’s data center Artificial Intelligence (AI) accelerator roadmap, components, vendor co-developments, custom designs and chiplets.
• Create high performance hardware/software interfaces and collaborate with software, verification, emulation, physical design, packaging and silicon validation stakeholders to ensure designs are complete, correct and performant.
• Identify and drive power, performance and area improvements for the modules owned and develop and contribute to the simulations tools.

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