RandD Engineer - Frontend Design Flow Synthesis And Methodology

Job Titles

R&D Engineer – Frontend Design Flow (Synthesis & Methodology).

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You have spent time deep in digital design and you understand that RTL is just the beginning. The real work starts when you need to synthesize it, optimize it, and make it meet PPA targets that matter. You know your way around Verilog or System Verilog well enough to spot what will cause problems downstream, and you have written enough scripts in Python, Tcl, Perl, or Shell to automate the repetitive parts so you can focus on the hard decisions.

You are comfortable digging into synthesis flows, timing reports, and constraint files. When something does not converge, you do not just re-run the tool. You ask why, trace it back, and figure out what needs to change. You like working with data, whether that means parsing logs, comparing PPA across runs, or building dashboards that help the team see what is happening.

You are curious about how EDA tools work, not just how to use them. At Synopsys, you will work on the frontend design flows that our customers and internal teams depend on, and you will have the chance to shape how synthesis and methodology get done.

What Youll Be Doing

• Ramp up on the Synopsys toolchain and independently run synthesis flows using Design Compiler and Fusion Compiler, plus static timing analysis flows using PrimeTime
• Develop and optimize frontend design methodologies tailored to Synopsys logic libraries, ensuring flows align with standard cell library capabilities and constraints
• Build and maintain robust synthesis and STA flows that improve design convergence across timing, power, and area dimensions
• Automate repetitive tasks and flow steps using Tcl, Python, or Shell scripting to increase efficiency and reduce manual errors
• Debug flow issues, analyse synthesis and timing reports, and resolve PPA bottlenecks that block design closure
• Contribute to QA and validation efforts for new standard cell library development, ensuring cells perform as expected in real design contexts
• Act as a bridge between tool development teams, Silicon IP teams, and customer design teams to align flow improvements with real-world needs
  
  

The Impact You Will Have

• Strengthen the competitiveness of Synopsys Silicon IP and standard cell libraries by proving out their performance in real synthesis and STA flows
• Improve design flow efficiency and quality, enabling internal teams and customers to close designs faster and with better PPA outcomes
• Help customers achieve their timing, power, and area targets more reliably by delivering methodologies and flows that work out of the box
• Enhance Synopsys tool adoption and effectiveness by making the tools easier to use and more predictable in customer hands
• Reduce design iteration cycles by catching library, constraint, and flow issues early in the process
• Enable efficient use of Synopsys EDA tools and standard cell libraries across a wide range of design teams and use cases
• Drive flow improvement initiatives that scale across multiple projects and customers, making a measurable difference in how designs get done
  
  

What Youll Need

• Bachelors or master’s degree in Electronics Engineering, VLSI, Computer Science, or related field
• Strong fundamentals in Digital Electronics and VLSI Design
• Solid understanding of RTL design using Verilog or System Verilog
• Proficiency in at least one scripting or programming language: Python, Tcl, Perl, or Shell scripting
• Experience with data analysis, log parsing, or report interpretation to drive flow optimization
• Knowledge of synthesis flows from RTL to gate-level is a strong advantage
• Familiarity with static timing analysis, timing constraints, SDC, or PPA optimization is a plus
  
  

Who You Are

• You have a strong analytical mindset, and you do not stop at surface-level answers when debugging a flow or timing issue
• You are detail-oriented enough to catch constraint mismatches, library usage errors, or report anomalies that others might miss
• You work well across teams, and you know how to translate between tool developers who think in features and design teams who think in outcomes
• You are curious and you pick up new EDA tools, standard cell libraries, and methodologies quickly because you care about how things work
• You are comfortable working in structured, automation-driven environments where repeatability and accuracy matter
• You can explain a technical trade-off or a synthesis result clearly in a team discussion without losing the nuance
  
  

Rewards And Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

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