Principal SoC RTL Design Engineer

About TylSemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

Thats what we solve. TylSemi builds the chiplet infrastructure IP — the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isnt a nice-to-have. Its the critical path.

Why Now

The Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

• Moores Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI — theyre all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
  
  

Translation: Were entering the market at exactly the moment when every major AI/HPC player needs what were building, and their alternatives are disappearing.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.
  
  

Remote-Friendly, Global Team

• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world-class design center in Bangalore
  
  

Move Fast, Ship Real Products

Were not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. Were building to win.

What We Value

• Ownership mindset. Youre not here to execute someone elses roadmap. Youre here to define it.
• Bias for action. We move fast. Analysis paralysis doesnt fly here.
• Deep technical expertise. This is hard engineering. We need people whove shipped real silicon and debugged real hardware.
• Low ego, high standards. We dont care about titles or politics. We care about results.
  
  

The Ask

If youre reading this, youre probably comfortable. You have a good job at a stable company with all the benefits.

Were asking you to walk away from that and bet on us.

Heres Why You Should

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what were building.
• The team has done this before. Weve built and exited semiconductor companies at scale. This isnt our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. Youre not optimizing someones ad click-through rate. Youre building the silicon infrastructure that powers AI.
  
  

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if youre the kind of person who wants to take the shot, wed love to talk.

READY TO JOIN?

Role Overview

We are looking for a highly skilled RTL Designer to develop high-performance, scalable, and power-efficient digital designs for next-generation SoCs and Chiplets targeting AI, HPC, and Networking applications. This role requires deep expertise in RTL design, micro-architecture, and integration of high-speed interfaces, along with a strong focus on quality, performance, and first-time silicon success.

Key Responsibilities

• Design and implement high-quality RTL for complex SoC components and subsystems
• Own micro-architecture definition and execution for performance-critical blocks
• Develop designs that scale across IP, subsystem, and full SoC integration
• Integrate and optimize high-speed IO protocols such as:

• PCIe / CXL
  
  

• Ethernet (various speeds)
  
  

• UCIe (chiplet interconnects)
• Ensure robust design practices for:
  
  

• Timing closure
  
  

• Power efficiency
  
  

• Area optimization
• Collaborate closely with architecture, DV, physical design, and firmware teams
• Drive design quality initiatives including lint, CDC, RDC, and formal verification
• Support emulation, prototyping, and silicon bring-up
• Contribute to building reusable design components and IPs across multiple programs
• Leverage automation and AI tools to improve RTL productivity and design quality
  
  
Required Qualifications


• Bachelor’s/Master’s degree in Electrical Engineering or related field
• 8+ years of experience in RTL design and micro-architecture
• Strong expertise in:
  
  

• Verilog/SystemVerilog
  
  

• Digital design fundamentals
  
  

• High-performance and low-power design techniques
  
  

• Experience designing for large SoCs in AI, HPC, or Networking domains
• Solid understanding of high-speed IO protocols: UCIe, PCIe, Ethernet
• Experience with multi-clock, high-bandwidth, and latency-sensitive designs
• Strong debugging and problem-solving skills
  
  

Preferred Qualifications

• Experience with memory interfaces (DDR, HBM, LPDDR)
• Familiarity with coherency protocols and interconnect fabrics
• Exposure to synthesis, STA, and physical design constraints
• Experience with emulation or FPGA prototyping
• Working knowledge of scripting (Python, Tcl)
  
  

Key Attributes

• Strong ownership and attention to detail
• Focus on quality and first-pass silicon success
• Ability to work across teams in a fast-paced environment
• Bias toward scalable, reusable, and clean design
  
  

Success Metrics

• High-quality RTL with minimal re-spins
• Successful integration into complex SoCs
• Performance, power, and area targets met
• Contribution to reusable IP and design frameworks

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