Principal Physical Design Engineer

Non-Volatile Memory IP Physical Design Lead

NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections and infrastructure for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets.

CTO/Frontend Innovation/NVM Design Technology Department is responsible for all embedded Non-Volatile Memory deployment across NXP business and product lines. Embedded NVM encompasses nearly all technology nodes and products which integrate Logic NVM, Flash or disruptive memory solutions (e.g. RRAM, MRAM). The implementation of Embedded NVM technologies that enhance application capabilities is a competitive advantage in the marketplace.

In this position, we are looking for Physical Design lead to join our NXP’s NVM IP design group in Bangalore, India.

Are you ready to lead the Physical design competence and drive the implementation and sign-off of advanced MRAM/RRAM NVM IPs in FinFET technology nodes? Can you develop efficient and automated implementation flows, and collaborate closely with the NVM design teams, NXP product development teams to deliver scalable, production‑ready NVM IP solutions across NXP’s diverse product portfolio, including automotive?

Scope Of Responsibilities/Expectations

As the NVM IP Back‑End Design Lead for our newly formed Bangalore team, you will be part of a global NVM design organization. You will lead the back‑end design competence for a wide range of disruptive NVM IPs targeting Automotive MCUs, MPUs, and beyond. Your responsibilities will include:

• Lead and perform all functions in RTL2GDS flow including Synthesis, Floor-Planning, Power Distribution, Clock Tree Synthesis, Place and Route, ECO’s, and Chip Finishing with Metal/Dummy Fill
• Run Physical Verification
• Leverage AI tools to develop efficient and automated Physical design flows
• Team up with NXP NVM design team in Bangalore, EU and US
• Mentor junior engineers growing in the NVM field
  
  

• BS or MS in Electronics or Electrical Engineering with +10 years of experience in place and route design
• Hands-on experience on quality-managed Analog-Mixed signals design flows, tools and methodologies (Cadence and Synopsys)
• Hands-on experience in scripting and flow automation
• Must show expertise in either Cadence or Synopsys tools; but it is preferrable to be flexible between the two toolsets
• Experience in 1X/FinFET nodes and below for Place & Route
• Knowledge of NVM technology, macro architecture and design is highly desired, but not mandatory
• Excellent communication skills with proven experience in international relationships and available for occasional travel.