Principal Logic Design Engineer - UALink IP Subsystem

Principal Logic Design Engineer – UALink IP/Subsystem

Experience

10–15 years

Job Summary

We are looking for a Principal Logic Design Engineer with strong expertise in high-performance interconnect and SoC/IP design to lead RTL and microarchitecture development for UALink-based IP/subsystems.

Key Responsibilities

• Lead architecture and RTL development for UALink IP/subsystems.
• Translate protocol and system requirements into scalable hardware architecture.
• Design high-bandwidth, low-latency data paths and control logic.
• Develop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability.
• Define interfaces between UALink and other SoC/interconnect components.
• Develop and review SystemVerilog RTL.
• Drive design optimization for performance, power, area, and latency.
• Work closely with verification, physical design, SoC integration, and firmware teams.
• Review design specifications and contribute to architectural decisions.
• Debug complex simulation and integration issues.
• Provide technical leadership and mentorship.

Required Skills

• Strong experience in RTL and microarchitecture development.
• Experience with high-speed interconnects and/or coherent fabrics.
• Strong understanding of computer architecture, networking/interconnect concepts, and data movement.
• Proficiency in SystemVerilog/Verilog.
• Strong understanding of CDC, reset architecture, performance, and hardware design methodology.

Preferred

• Direct UALink experience.
• Experience with PCIe, CXL, CCIX, CHI, Ethernet, or similar protocols.
• Experience in AI/accelerator or high-performance compute systems.